Jose A. Tierno

Person

Stamford, CT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Data detection on serial communication links
- Patent number 12,028,075
- Issue date Jul 2, 2024
- Apple Inc.
- Vishal Varma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock frequency limiter
- Patent number 12,021,538
- Issue date Jun 25, 2024
- Apple Inc.
- Jose A. Tierno
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Serial data receiver circuit with dither assisted equalization
- Patent number 11,757,681
- Issue date Sep 12, 2023
- Apple Inc.
- Jose A. Tierno
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Time-division multiplexed neurosynaptic module with implicit memory...
- Patent number 11,295,201
- Issue date Apr 5, 2022
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Producing spike-timing dependent plasticity in a neuromorphic netwo...
- Patent number 11,270,192
- Issue date Mar 8, 2022
- International Business Machines Corporation
- Daniel J. Friedman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Producing spike-timing dependent plasticity in a neuromorphic netwo...
- Patent number 11,232,345
- Issue date Jan 25, 2022
- International Business Machines Corporation
- Daniel J. Friedman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip to chip interface with scalable bandwidth
- Patent number 11,023,403
- Issue date Jun 1, 2021
- Apple Inc.
- Jafar Savoj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable and customizable general-purpose circuits for neural...
- Patent number 10,810,487
- Issue date Oct 20, 2020
- International Business Machines Corporation
- Bernard V. Brezzo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable and customizable general-purpose circuits for neural...
- Patent number 10,628,732
- Issue date Apr 21, 2020
- International Business Machines Corporation
- Bernard V. Brezzo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip to chip interface with scalable bandwidth
- Patent number 10,521,391
- Issue date Dec 31, 2019
- Apple Inc.
- Jafar Savoj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Time-division multiplexed neurosynaptic module with implicit memory...
- Patent number 10,331,998
- Issue date Jun 25, 2019
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Producing spike-timing dependent plasticity in a neuromorphic netwo...
- Patent number 9,953,261
- Issue date Apr 24, 2018
- International Business Machines Corporation
- Daniel J. Friedman
- G11 - INFORMATION STORAGE
Information Patent Grant
Producing spike-timing dependent plasticity in a neuromorphic netwo...
- Patent number 9,946,969
- Issue date Apr 17, 2018
- International Business Machines Corporation
- Daniel J. Friedman
- G11 - INFORMATION STORAGE
Information Patent Grant
Time-division multiplexed neurosynaptic module with implicit memory...
- Patent number 9,818,058
- Issue date Nov 14, 2017
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Loop parameter sensor using repetitive phase errors
- Patent number 9,800,251
- Issue date Oct 24, 2017
- International Business Machines Corporation
- Mark Ferriss
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reconfigurable and customizable general-purpose circuits for neural...
- Patent number 9,460,383
- Issue date Oct 4, 2016
- International Business Machines Corporation
- Bernard V. Brezzo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Time-division multiplexed neurosynaptic module with implicit memory...
- Patent number 9,373,073
- Issue date Jun 21, 2016
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Producing spike-timing dependent plasticity in a neuromorphic netwo...
- Patent number 9,269,042
- Issue date Feb 23, 2016
- International Business Machines Corporation
- Daniel J. Friedman
- G11 - INFORMATION STORAGE
Information Patent Grant
Time-division multiplexed neurosynaptic module with implicit memory...
- Patent number 9,239,984
- Issue date Jan 19, 2016
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sub-rate low-swing data receiver
- Patent number 9,240,789
- Issue date Jan 19, 2016
- International Business Machines Corporation
- Daniel J. Friedman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Calibration schemes for charge-recycling stacked voltage domains
- Patent number 9,207,695
- Issue date Dec 8, 2015
- GLOBALFOUNDRIES Inc.
- Daniel Friedman
- G05 - CONTROLLING REGULATING
Information Patent Grant
Loop parameter sensor using repetitive phase errors
- Patent number 9,157,950
- Issue date Oct 13, 2015
- International Business Machines Corporation
- Mark Ferriss
- G01 - MEASURING TESTING
Information Patent Grant
Transimpedance amplifier
- Patent number 8,994,457
- Issue date Mar 31, 2015
- International Business Machines Corporation
- Jonathan E. Proesel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Soft error protection in individual memory devices
- Patent number 8,949,685
- Issue date Feb 3, 2015
- International Business Machines Corporation
- Douglas J. Joseph
- G11 - INFORMATION STORAGE
Information Patent Grant
Reconfigurable and customizable general-purpose circuits for neural...
- Patent number 8,898,097
- Issue date Nov 25, 2014
- International Business Machines Corporation
- Bernard V. Brezzo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable and customizable general-purpose circuits for neural...
- Patent number 8,856,055
- Issue date Oct 7, 2014
- International Business Machines Corporation
- Bernard V. Brezzo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Calibration schemes for charge-recycling stacked voltage domains
- Patent number 8,797,084
- Issue date Aug 5, 2014
- International Business Machines Corporation
- Daniel Friedman
- G05 - CONTROLLING REGULATING
Information Patent Grant
Fully decoupled LC-tank based oscillator topology for low phase noi...
- Patent number 8,773,215
- Issue date Jul 8, 2014
- International Business Machines Corporation
- Bodhisatwa Sadhu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Hybrid phase-locked loop architectures
- Patent number 8,704,566
- Issue date Apr 22, 2014
- International Business Machines Corporation
- Herschel A. Ainspan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Hybrid phase-locked loop architectures
- Patent number 8,704,567
- Issue date Apr 22, 2014
- International Business Machines Corporation
- Herschel A. Ainspan
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Clock Frequency Limiter
- Publication number 20240305303
- Publication date Sep 12, 2024
- Apple Inc.
- Jose A. Tierno
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Data Detection on Serial Communication Links
- Publication number 20240283436
- Publication date Aug 22, 2024
- Apple Inc.
- Vishal Varma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Encoding and Decoding for PAM Transmitter and Receiver
- Publication number 20240097877
- Publication date Mar 21, 2024
- Apple Inc.
- Jose A. Tierno
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Data Detection on Serial Communication Links
- Publication number 20230387898
- Publication date Nov 30, 2023
- Apple Inc.
- Vishal Varma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock Frequency Limiter
- Publication number 20230378962
- Publication date Nov 23, 2023
- Apple Inc.
- Jose A. Tierno
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CHIP TO CHIP INTERFACE WITH SCALABLE BANDWIDTH
- Publication number 20200183874
- Publication date Jun 11, 2020
- Apple Inc.
- Jafar Savoj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY...
- Publication number 20190228289
- Publication date Jul 25, 2019
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWO...
- Publication number 20180197074
- Publication date Jul 12, 2018
- International Business Machines Corporation
- Daniel J. Friedman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWO...
- Publication number 20180197073
- Publication date Jul 12, 2018
- International Business Machines Corporation
- Daniel J. Friedman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL...
- Publication number 20160358067
- Publication date Dec 8, 2016
- International Business Machines Corporation
- Bernard V. Brezzo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL...
- Publication number 20160292569
- Publication date Oct 6, 2016
- International Business Machines Corporation
- Bernard V. Brezzo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY...
- Publication number 20160260008
- Publication date Sep 8, 2016
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL...
- Publication number 20160247063
- Publication date Aug 25, 2016
- International Business Machines Corporation
- Bernard V. Brezzo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWO...
- Publication number 20160224887
- Publication date Aug 4, 2016
- International Business Machines Corporation
- Daniel J. Friedman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWO...
- Publication number 20160224890
- Publication date Aug 4, 2016
- International Business Machines Corporation
- Daniel J. Friedman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY...
- Publication number 20160110640
- Publication date Apr 21, 2016
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOOP PARAMETER SENSOR USING REPETITIVE PHASE ERRORS
- Publication number 20160036452
- Publication date Feb 4, 2016
- International Business Machines Corporation
- Mark Ferriss
- G01 - MEASURING TESTING
Information Patent Application
SUB-RATE LOW-SWING DATA RECEIVER
- Publication number 20150303920
- Publication date Oct 22, 2015
- International Business Machines Corporation
- Daniel J. Friedman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CALIBRATION SCHEMES FOR CHARGE-RECYCLING STACKED VOLTAGE DOMAINS
- Publication number 20150301541
- Publication date Oct 22, 2015
- International Business Machines Corporation
- Daniel Friedman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY...
- Publication number 20140180984
- Publication date Jun 26, 2014
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY...
- Publication number 20140180987
- Publication date Jun 26, 2014
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CALIBRATION SCHEMES FOR CHARGE-RECYCLING STACKED VOLTAGE DOMAINS
- Publication number 20140176198
- Publication date Jun 26, 2014
- International Business Machines Corporation
- Daniel Friedman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HYBRID PHASE-LOCKED LOOP ARCHITECTURES
- Publication number 20140070856
- Publication date Mar 13, 2014
- International Business Machines Corporation
- Herschel A. Ainspan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HYBRID PHASE-LOCKED LOOP ARCHITECTURES
- Publication number 20140070855
- Publication date Mar 13, 2014
- International Business Machines Corporation
- Herschel A. Ainspan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TRANSIMPEDANCE AMPLIFIER
- Publication number 20140049323
- Publication date Feb 20, 2014
- International Business Machines Corporation
- Jonathan E. Proesel
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Application
PLL BANDWIDTH CORRECTION WITH OFFSET COMPENSATION
- Publication number 20130307588
- Publication date Nov 21, 2013
- International Business Machines Corporation
- Mark A. Ferriss
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
VARACTOR TUNING CONTROL USING REDUNDANT NUMBERING
- Publication number 20130076449
- Publication date Mar 28, 2013
- International Business Machines Corporation
- Herschel A. Ainspan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FULLY DECOUPLED LC-TANK BASED OSCILLATOR TOPOLOGY FOR LOW PHASE NOI...
- Publication number 20130063218
- Publication date Mar 14, 2013
- International Business Machines Corporation
- BODHISATWA SADHU
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLL BANDWIDTH CORRECTION WITH OFFSET COMPENSATION
- Publication number 20130063192
- Publication date Mar 14, 2013
- International Business Machines Corporation
- Mark A. Ferriss
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
REDUCING PHASE LOCKED LOOP PHASE LOCK TIME
- Publication number 20130057327
- Publication date Mar 7, 2013
- International Business Machines Corporation
- MARK FERRISS
- H03 - BASIC ELECTRONIC CIRCUITRY

Jose A. Tierno

Person

Patents Grantslast 30 patents

Data detection on serial communication links

Clock frequency limiter

Serial data receiver circuit with dither assisted equalization

Time-division multiplexed neurosynaptic module with implicit memory...

Producing spike-timing dependent plasticity in a neuromorphic netwo...

Producing spike-timing dependent plasticity in a neuromorphic netwo...

Chip to chip interface with scalable bandwidth

Reconfigurable and customizable general-purpose circuits for neural...

Reconfigurable and customizable general-purpose circuits for neural...

Chip to chip interface with scalable bandwidth

Time-division multiplexed neurosynaptic module with implicit memory...

Producing spike-timing dependent plasticity in a neuromorphic netwo...

Producing spike-timing dependent plasticity in a neuromorphic netwo...

Time-division multiplexed neurosynaptic module with implicit memory...

Loop parameter sensor using repetitive phase errors

Reconfigurable and customizable general-purpose circuits for neural...

Time-division multiplexed neurosynaptic module with implicit memory...

Producing spike-timing dependent plasticity in a neuromorphic netwo...

Time-division multiplexed neurosynaptic module with implicit memory...

Sub-rate low-swing data receiver

Calibration schemes for charge-recycling stacked voltage domains

Loop parameter sensor using repetitive phase errors

Transimpedance amplifier

Soft error protection in individual memory devices

Reconfigurable and customizable general-purpose circuits for neural...

Reconfigurable and customizable general-purpose circuits for neural...

Calibration schemes for charge-recycling stacked voltage domains

Fully decoupled LC-tank based oscillator topology for low phase noi...

Hybrid phase-locked loop architectures

Hybrid phase-locked loop architectures

Patents Applicationslast 30 patents

Clock Frequency Limiter

Data Detection on Serial Communication Links

Encoding and Decoding for PAM Transmitter and Receiver

Data Detection on Serial Communication Links

Clock Frequency Limiter

CHIP TO CHIP INTERFACE WITH SCALABLE BANDWIDTH

TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY...

PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWO...

PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWO...

RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL...

RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL...

TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY...

RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL...

PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWO...

PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWO...

TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY...

LOOP PARAMETER SENSOR USING REPETITIVE PHASE ERRORS

SUB-RATE LOW-SWING DATA RECEIVER

CALIBRATION SCHEMES FOR CHARGE-RECYCLING STACKED VOLTAGE DOMAINS

TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY...

TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY...

CALIBRATION SCHEMES FOR CHARGE-RECYCLING STACKED VOLTAGE DOMAINS

HYBRID PHASE-LOCKED LOOP ARCHITECTURES

HYBRID PHASE-LOCKED LOOP ARCHITECTURES

TRANSIMPEDANCE AMPLIFIER

PLL BANDWIDTH CORRECTION WITH OFFSET COMPENSATION

VARACTOR TUNING CONTROL USING REDUNDANT NUMBERING

FULLY DECOUPLED LC-TANK BASED OSCILLATOR TOPOLOGY FOR LOW PHASE NOI...

PLL BANDWIDTH CORRECTION WITH OFFSET COMPENSATION

REDUCING PHASE LOCKED LOOP PHASE LOCK TIME