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Jose V. Siles
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Pasadena, CA, US
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Patents Grants
last 30 patents
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Patent Grant
Wafer-to-wafer alignment method
Patent number
10,100,858
Issue date
Oct 16, 2018
California Institute of Technology
Cecile Jung-Kubiak
F16 - ENGINEERING ELEMENTS AND UNITS GENERAL MEASURES FOR PRODUCING AND MAINT...
Information
Patent Grant
340 GHz multipixel transceiver
Patent number
9,791,321
Issue date
Oct 17, 2017
California Institute of Technology
Goutam Chattopadhyay
G01 - MEASURING TESTING
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Patent Grant
Silicon alignment pins: an easy way to realize a wafer-to-wafer ali...
Patent number
9,512,863
Issue date
Dec 6, 2016
California Institute of Technology
Cecile Jung-Kubiak
F16 - ENGINEERING ELEMENTS AND UNITS GENERAL MEASURES FOR PRODUCING AND MAINT...
Patents Applications
last 30 patents
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Patent Application
WAFER-TO-WAFER ALIGNMENT METHOD
Publication number
20170045065
Publication date
Feb 16, 2017
California Institute of Technology
Cecile JUNG-KUBIAK
F16 - ENGINEERING ELEMENTS AND UNITS GENERAL MEASURES FOR PRODUCING AND MAINT...
Information
Patent Application
SILICON ALIGNMENT PINS: AN EASY WAY TO REALIZE A WAFER-TO-WAFER ALI...
Publication number
20140147192
Publication date
May 29, 2014
California Institute of Technology
Cecile Jung-Kubiak
Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information
Patent Application
ON-CHIP POWER-COMBINING FOR HIGH-POWER SCHOTTKY DIODE BASED FREQUEN...
Publication number
20130229210
Publication date
Sep 5, 2013
California Institute of Technology
Jose V. Siles
H01 - BASIC ELECTRIC ELEMENTS