Joseph Davis

Follow

Person

Mesa, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of obfuscating digital logic circuits using threshold voltage
- Patent number 9,876,503
- Issue date Jan 23, 2018
- Arixona Board of Regents on Behalf of Arizona State University
- Sarma Vrudhula
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF OBFUSCATING DIGITAL LOGIC CIRCUITS USING THRESHOLD VOLTAGE
- Publication number 20170187382
- Publication date Jun 29, 2017
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- H03 - BASIC ELECTRONIC CIRCUITRY