Joseph H. Salmon

Person

Placeville, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Transceiver clock architecture with transmit PLL and receive slave...
- Patent number 9,237,000
- Issue date Jan 12, 2016
- Intel Corporation
- Aaron Martin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory controller functionalities to support data swizzling
- Patent number 8,595,428
- Issue date Nov 26, 2013
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for training a memory signal via an error sign...
- Patent number 8,533,538
- Issue date Sep 10, 2013
- Intel Corporation
- Santanu Chaudhuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for interfacing with heterogeneous dual in-lin...
- Patent number 8,495,330
- Issue date Jul 23, 2013
- Intel Corporation
- George Vergis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing the size of memory devices used for error correction cod...
- Patent number 8,468,433
- Issue date Jun 18, 2013
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Grant
Bus frequency adjustment circuitry for use in a dynamic random acce...
- Patent number 8,458,507
- Issue date Jun 4, 2013
- Intel Corporation
- Joe Salmon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reliability, availability, and serviceability solution for memory t...
- Patent number 8,392,796
- Issue date Mar 5, 2013
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reliability, availability, and serviceability solutions for memory...
- Patent number 8,132,074
- Issue date Mar 6, 2012
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing the size of memory devices used for error correction cod...
- Patent number 8,108,761
- Issue date Jan 31, 2012
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Grant
Nibble de-skew method, apparatus, and system
- Patent number 7,954,001
- Issue date May 31, 2011
- Intel Corporation
- Aaron K. Martin
- G11 - INFORMATION STORAGE
Information Patent Grant
Extended synchronized clock
- Patent number 7,751,274
- Issue date Jul 6, 2010
- Intel Corporation
- Navneet Dour
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clocking architecture using a bidirectional clock port
- Patent number 7,555,670
- Issue date Jun 30, 2009
- Intel Corporation
- Ravindran Mohanavelu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for power efficient and scalable memory interface
- Patent number 7,459,938
- Issue date Dec 2, 2008
- Intel Corporation
- Hing Yan To
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Countering power resonance
- Patent number 7,447,929
- Issue date Nov 4, 2008
- Intel Corporation
- James A. McCall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Nibble de-skew method, apparatus, and system
- Patent number 7,401,246
- Issue date Jul 15, 2008
- Intel Corporation
- Aaron K. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latency normalization by balancing early and late clocks
- Patent number 7,324,403
- Issue date Jan 29, 2008
- Intel Corporation
- Hing Yan To
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for optimizing strobe to clock relationship
- Patent number 7,307,900
- Issue date Dec 11, 2007
- Intel Corporation
- Joe Salmon
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for power efficient and scalable memory interface
- Patent number 7,243,176
- Issue date Jul 10, 2007
- Intel Corporation
- Hing Yan To
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Slave I/O driver calibration using error-nulling master reference
- Patent number 7,194,559
- Issue date Mar 20, 2007
- Intel Corporation
- Joseph H. Salmon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for optimizing timing for a multi-drop bus
- Patent number 7,117,401
- Issue date Oct 3, 2006
- Intel Corporation
- Joseph H. Salmon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for optimizing timing for a multi-drop bus
- Patent number 6,973,603
- Issue date Dec 6, 2005
- Intel Corporation
- Joseph H. Salmon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synthesis of a synchronization clock
- Patent number 6,941,484
- Issue date Sep 6, 2005
- Intel Corporation
- Hing Y. To
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and method for calibrating DRAM pullup Ron to pulldown Ron
- Patent number 6,885,959
- Issue date Apr 26, 2005
- Intel Corporation
- Joseph H. Salmon
- G11 - INFORMATION STORAGE
Information Patent Grant
Fast re-synchronization of independent domain clocks after powerdow...
- Patent number 6,662,305
- Issue date Dec 9, 2003
- Intel Corporation
- Joe H. Salmon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing IO timing in a delay locked system using separate transmit...
- Patent number 6,421,801
- Issue date Jul 16, 2002
- Intel Corporation
- John T. Maddux
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for testing high speed input paths
- Patent number 6,381,722
- Issue date Apr 30, 2002
- Intel Corporation
- Joseph H. Salmon
- G01 - MEASURING TESTING
Information Patent Grant
Memory controller with a plurality of memory address buses
- Patent number 6,260,105
- Issue date Jul 10, 2001
- Intel Corporation
- Mike W. Williams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for independent power-up sequencing of a multi-voltage chip
- Patent number 6,236,250
- Issue date May 22, 2001
- Intel Corporation
- Joseph H. Salmon
- G05 - CONTROLLING REGULATING
Information Patent Grant
Method and apparatus for operating a synchronous strobe bus
- Patent number 6,195,759
- Issue date Feb 27, 2001
- Intel Corporation
- Joseph H. Salmon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing leakage currents in an I/O buffer
- Patent number 5,892,377
- Issue date Apr 6, 1999
- Intel Corporation
- Robert James Johnston
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
RELIABILITY, AVAILABILITY, AND SERVICEABILITY SOLUTION FOR MEMORY T...
- Publication number 20120131414
- Publication date May 24, 2012
- Intel Corporation
- KULJIT S. BAINS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZING THE SIZE OF MEMORY DEVICES USED FOR ERROR CORRECTION COD...
- Publication number 20120124451
- Publication date May 17, 2012
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR TRAINING A MEMORY SIGNAL VIA AN ERROR SIGN...
- Publication number 20110320867
- Publication date Dec 29, 2011
- Santanu Chaudhuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR INTERFACING WITH HETEROGENEOUS DUAL IN-LIN...
- Publication number 20110246712
- Publication date Oct 6, 2011
- George Vergis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER FUNCTIONALITIES TO SUPPORT DATA SWIZZLING
- Publication number 20110153925
- Publication date Jun 23, 2011
- KULJIT S. BAINS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUS FREQUENCY ADJUSTMENT CIRCUITRY FOR USE IN A DYNAMIC RANDOM ACCE...
- Publication number 20090327792
- Publication date Dec 31, 2009
- Intel Corporation
- Joe Salmon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RELIABILITY, AVAILABILITY, AND SERVICEABILITY SOLUTIONS FOR MEMORY...
- Publication number 20090132888
- Publication date May 21, 2009
- KULJIT S. BAINS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZING THE SIZE OF MEMORY DEVICES USED FOR ERROR CORRECTION COD...
- Publication number 20090055714
- Publication date Feb 26, 2009
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Application
NIBBLE DE-SKEW METHOD, APPARATUS, AND SYSTEM
- Publication number 20080244303
- Publication date Oct 2, 2008
- Aaron K. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory system with a configurable number of read data bits
- Publication number 20080151591
- Publication date Jun 26, 2008
- Intel Corporation
- Kevin J. Doran
- G11 - INFORMATION STORAGE
Information Patent Application
Extended synchronized clock
- Publication number 20080065922
- Publication date Mar 13, 2008
- Navneet Dour
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Transceiver clock architecture with transmit PLL and receive slave...
- Publication number 20070291828
- Publication date Dec 20, 2007
- Aaron Martin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Clocking architecture using a bi-directional reference clock
- Publication number 20070091712
- Publication date Apr 26, 2007
- Intel Corporation
- Ravindran Mohanavelu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for power efficient and scalable memory interface
- Publication number 20070079034
- Publication date Apr 5, 2007
- Hing Yan To
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Countering power resonance
- Publication number 20070074055
- Publication date Mar 29, 2007
- James A. McCall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Nibble de-skew method, apparatus, and system
- Publication number 20070006011
- Publication date Jan 4, 2007
- Intel Corporation
- Aaron K. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for optimizing strobe to clock relationship
- Publication number 20060114742
- Publication date Jun 1, 2006
- Joe Salmon
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for power efficient and scalable memory interface
- Publication number 20060101167
- Publication date May 11, 2006
- Hing Yan To
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Latency normalization by balancing early and late clocks
- Publication number 20060067155
- Publication date Mar 30, 2006
- Hing Yan To
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for optimizing timing for a multi-drop bus
- Publication number 20050195677
- Publication date Sep 8, 2005
- Joseph H. Salmon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit and method for calibrating dram pullup Ron to pulldown Ron
- Publication number 20040083070
- Publication date Apr 29, 2004
- Intel Corporation
- Joseph H. Salmon
- G01 - MEASURING TESTING
Information Patent Application
Slave I/O driver calibration using error-nulling master reference
- Publication number 20040044808
- Publication date Mar 4, 2004
- Intel Corporation (a Delaware corporation)
- Joseph H. Salmon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for optimizing timing for a multi-drop bus
- Publication number 20040003331
- Publication date Jan 1, 2004
- Joseph H. Salmon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for capturing data from a memory subsystem
- Publication number 20030167417
- Publication date Sep 4, 2003
- Hing Y. To
- G06 - COMPUTING CALCULATING COUNTING

Joseph H. Salmon

Person

Patents Grantslast 30 patents

Transceiver clock architecture with transmit PLL and receive slave...

Memory controller functionalities to support data swizzling

Method and apparatus for training a memory signal via an error sign...

Method and apparatus for interfacing with heterogeneous dual in-lin...

Optimizing the size of memory devices used for error correction cod...

Bus frequency adjustment circuitry for use in a dynamic random acce...

Reliability, availability, and serviceability solution for memory t...

Reliability, availability, and serviceability solutions for memory...

Optimizing the size of memory devices used for error correction cod...

Nibble de-skew method, apparatus, and system

Extended synchronized clock

Clocking architecture using a bidirectional clock port

Method and apparatus for power efficient and scalable memory interface

Countering power resonance

Nibble de-skew method, apparatus, and system

Latency normalization by balancing early and late clocks

Method and apparatus for optimizing strobe to clock relationship

Method and apparatus for power efficient and scalable memory interface

Slave I/O driver calibration using error-nulling master reference

Method and apparatus for optimizing timing for a multi-drop bus

Method and apparatus for optimizing timing for a multi-drop bus

Synthesis of a synchronization clock

Circuit and method for calibrating DRAM pullup Ron to pulldown Ron

Fast re-synchronization of independent domain clocks after powerdow...

Testing IO timing in a delay locked system using separate transmit...

Method and apparatus for testing high speed input paths

Memory controller with a plurality of memory address buses

Circuit for independent power-up sequencing of a multi-voltage chip

Method and apparatus for operating a synchronous strobe bus

Method and apparatus for reducing leakage currents in an I/O buffer

Patents Applicationslast 30 patents

RELIABILITY, AVAILABILITY, AND SERVICEABILITY SOLUTION FOR MEMORY T...

OPTIMIZING THE SIZE OF MEMORY DEVICES USED FOR ERROR CORRECTION COD...

METHOD AND APPARATUS FOR TRAINING A MEMORY SIGNAL VIA AN ERROR SIGN...

METHOD AND APPARATUS FOR INTERFACING WITH HETEROGENEOUS DUAL IN-LIN...

MEMORY CONTROLLER FUNCTIONALITIES TO SUPPORT DATA SWIZZLING

BUS FREQUENCY ADJUSTMENT CIRCUITRY FOR USE IN A DYNAMIC RANDOM ACCE...

RELIABILITY, AVAILABILITY, AND SERVICEABILITY SOLUTIONS FOR MEMORY...

OPTIMIZING THE SIZE OF MEMORY DEVICES USED FOR ERROR CORRECTION COD...

NIBBLE DE-SKEW METHOD, APPARATUS, AND SYSTEM

Memory system with a configurable number of read data bits

Extended synchronized clock

Transceiver clock architecture with transmit PLL and receive slave...

Clocking architecture using a bi-directional reference clock

Method and apparatus for power efficient and scalable memory interface

Countering power resonance

Nibble de-skew method, apparatus, and system

Method and apparatus for optimizing strobe to clock relationship

Method and apparatus for power efficient and scalable memory interface

Latency normalization by balancing early and late clocks

Method and apparatus for optimizing timing for a multi-drop bus

Circuit and method for calibrating dram pullup Ron to pulldown Ron

Slave I/O driver calibration using error-nulling master reference

Method and apparatus for optimizing timing for a multi-drop bus

Method and apparatus for capturing data from a memory subsystem