Joseph Huang

Person

Morgan Hill, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
On-die input reference voltage with self-calibrating duty cycle cor...
- Patent number 9,711,189
- Issue date Jul 18, 2017
- Altera Corporation
- Bonnie I. Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable high-speed I/O interface
- Patent number 9,473,145
- Issue date Oct 18, 2016
- Altera Corporation
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple data rate interface architecture
- Patent number 9,166,589
- Issue date Oct 20, 2015
- Altera Corporation
- Philip Pan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit design technique for DQS enable/disable calibration
- Patent number 9,158,873
- Issue date Oct 13, 2015
- Altera Corporation
- Yan Chong
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for memory controller reference voltage calibra...
- Patent number 9,111,603
- Issue date Aug 18, 2015
- Altera Corporation
- Xiaobao Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Adjustable drive strength input-output buffer circuitry
- Patent number 9,099,999
- Issue date Aug 4, 2015
- Altera Corporation
- Bonnie I. Wang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Digital PVT compensation for delay chain
- Patent number 9,059,716
- Issue date Jun 16, 2015
- Altera Corporation
- Pradeep Nagarajan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable high-speed I/O interface
- Patent number 8,829,948
- Issue date Sep 9, 2014
- Altera Corporation
- Bonnie I. Wang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Circuit design technique for DQS enable/disable calibration
- Patent number 8,787,097
- Issue date Jul 22, 2014
- Altera Corporation
- Yan Chong
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for minimizing skew between signals
- Patent number 8,779,754
- Issue date Jul 15, 2014
- Altera Corporation
- Yan Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable delay circuitry with compensated delay
- Patent number 8,723,575
- Issue date May 13, 2014
- Altera Corporation
- Ee Mei Ooi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital PVT compensation for delay chain
- Patent number 8,680,905
- Issue date Mar 25, 2014
- Altera Corporation
- Pradeep Nagarajan
- G11 - INFORMATION STORAGE
Information Patent Grant
Write-leveling implementation in programmable logic devices
- Patent number 8,671,303
- Issue date Mar 11, 2014
- Altera Corporation
- Yan Chong
- G11 - INFORMATION STORAGE
Information Patent Grant
Duty cycle correction circuit for memory interfaces in integrated c...
- Patent number 8,624,647
- Issue date Jan 7, 2014
- Altera Corporation
- Yan Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High performance memory interface circuit architecture
- Patent number 8,593,195
- Issue date Nov 26, 2013
- Altera Corporation
- Joseph Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple data rate interface architecture
- Patent number 8,575,957
- Issue date Nov 5, 2013
- Altera Corporation
- Philip Pan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Variation compensation circuitry for memory interface
- Patent number 8,565,034
- Issue date Oct 22, 2013
- Altera Corporation
- Sean Shau-Tu Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable output buffer
- Patent number 8,531,205
- Issue date Sep 10, 2013
- Altera Corporation
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable high-speed interface
- Patent number 8,487,665
- Issue date Jul 16, 2013
- Altera Corporation
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for buffering single-ended and differential signals
- Patent number 8,400,186
- Issue date Mar 19, 2013
- Altera Corporation
- Xiaobao Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable input-output (I/O) circuitry with pre-emphasis circuitry
- Patent number 8,390,315
- Issue date Mar 5, 2013
- Altera Corporation
- Xiaobao Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High-performance memory interface circuit architecture
- Patent number 8,305,121
- Issue date Nov 6, 2012
- Altera Corporation
- Joseph Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for generating PVT compensated phase offset to improve a...
- Patent number 8,237,475
- Issue date Aug 7, 2012
- Altera Corporation
- Pradeep Nagarajan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for providing multiple delay paths in a delay circuit
- Patent number 8,159,277
- Issue date Apr 17, 2012
- Altera Corporation
- Pradeep Nagarajan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for providing reduced duty cycle distortion
- Patent number 8,130,016
- Issue date Mar 6, 2012
- Altera Corporation
- Pradeep Nagarajan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Write-leveling implementation in programmable logic devices
- Patent number 8,122,275
- Issue date Feb 21, 2012
- Altera Corporation
- Yan Chong
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple data rate interface architecture
- Patent number 8,098,082
- Issue date Jan 17, 2012
- Altera Corporation
- Philip Pan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Postamble timing for DDR memories
- Patent number 7,990,783
- Issue date Aug 2, 2011
- Altera Corporation
- Philip Clarke
- G11 - INFORMATION STORAGE
Information Patent Grant
Read-leveling implementations for DDR3 applications on an FPGA
- Patent number 7,990,786
- Issue date Aug 2, 2011
- Altera Corporation
- Michael H. M. Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
PVT compensated auto-calibration scheme for DDR3
- Patent number 7,983,094
- Issue date Jul 19, 2011
- Altera Corporation
- Manoj B. Roge
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Programmable High-Speed I/O Interface
- Publication number 20170005662
- Publication date Jan 5, 2017
- Altera Corporation
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable High-Speed I/O Interface
- Publication number 20170005661
- Publication date Jan 5, 2017
- Altera Corporation
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROGRAMMABLE HIGH-SPEED I/O INTERFACE
- Publication number 20140340125
- Publication date Nov 20, 2014
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTIPLE DATA RATE INTERFACE ARCHITECTURE
- Publication number 20140049287
- Publication date Feb 20, 2014
- Altera Corporation
- Philip Pan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROGRAMMABLE HIGH-SPEED I/O INTERFACE
- Publication number 20130278290
- Publication date Oct 24, 2013
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTIPLE DATA RATE INTERFACE ARCHITECTURE
- Publication number 20120146700
- Publication date Jun 14, 2012
- Altera Corporation
- Philip Pan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES
- Publication number 20120106264
- Publication date May 3, 2012
- Altera Corporation
- Yan Chong
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMABLE HIGH-SPEED INTERFACE
- Publication number 20110227606
- Publication date Sep 22, 2011
- ALTERA CORPORATION
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND APPARATUS FOR MINIMIZING SKEW BETWEEN SIGNALS
- Publication number 20110221497
- Publication date Sep 15, 2011
- Yan Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DUTY CYCLE CORRECTION CIRCUIT FOR MEMORY INTERFACES IN INTEGRATED C...
- Publication number 20110175657
- Publication date Jul 21, 2011
- Yan Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Techniques for Providing Reduced Duty Cycle Distortion
- Publication number 20110074477
- Publication date Mar 31, 2011
- Altera Corporation
- Pradeep Nagarajan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROGRAMMABLE HIGH-SPEED INTERFACE
- Publication number 20100045349
- Publication date Feb 25, 2010
- Altera Corporation
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA
- Publication number 20090296503
- Publication date Dec 3, 2009
- Altera Corporation
- Michael H.M. Chu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA
- Publication number 20080291758
- Publication date Nov 27, 2008
- Altera Corporation
- Michael H.M. Chu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES
- Publication number 20080201597
- Publication date Aug 21, 2008
- Altera Corporation
- Yan Chong
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMABLE HIGH-SPEED INTERFACE
- Publication number 20080186056
- Publication date Aug 7, 2008
- Altera Corporation
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SOFT ERROR LOCATION AND SENSITIVITY DETECTION FOR PROGRAMMABLE DEVICES
- Publication number 20070283193
- Publication date Dec 6, 2007
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Read-Side Calibration for Data Interface
- Publication number 20070282555
- Publication date Dec 6, 2007
- Altera Corporation
- Yan Chong
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Write-Side Calibration for Data Interface
- Publication number 20070277071
- Publication date Nov 29, 2007
- Altera Corporation
- Yan Chong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for deploying an SQL procedure
- Publication number 20070143249
- Publication date Jun 21, 2007
- International Business Machines Corporation
- Margaret Ann Bernal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Supporting multiple versions of a routine
- Publication number 20060288052
- Publication date Dec 21, 2006
- Yao-Ching Stephen Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable high speed interface
- Publication number 20060220703
- Publication date Oct 5, 2006
- Altera Corporation
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Loop circuitry with low-pass noise filter
- Publication number 20060164139
- Publication date Jul 27, 2006
- Yan Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Supply voltage detection circuit
- Publication number 20050253626
- Publication date Nov 17, 2005
- Yan Chong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable I/O element circuit for high speed logic devices
- Publication number 20050162187
- Publication date Jul 28, 2005
- Khai Nguyen
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Application
Programmable high speed I/O interface
- Publication number 20050134332
- Publication date Jun 23, 2005
- Altera Corporation
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic array integrated circuits
- Publication number 20040066212
- Publication date Apr 8, 2004
- Altera Corporation
- Richard G. Cliff
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic array integrated circuit devices
- Publication number 20030128051
- Publication date Jul 10, 2003
- Richard G. Cliff
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable high speed I/O interface
- Publication number 20030042941
- Publication date Mar 6, 2003
- Altera Corporation
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic array integrated circuit devices
- Publication number 20030016053
- Publication date Jan 23, 2003
- Richard G. Cliff
- H03 - BASIC ELECTRONIC CIRCUITRY

Joseph Huang

Person

Patents Grantslast 30 patents

On-die input reference voltage with self-calibrating duty cycle cor...

Programmable high-speed I/O interface

Multiple data rate interface architecture

Circuit design technique for DQS enable/disable calibration

Systems and methods for memory controller reference voltage calibra...

Adjustable drive strength input-output buffer circuitry

Digital PVT compensation for delay chain

Programmable high-speed I/O interface

Circuit design technique for DQS enable/disable calibration

Method and apparatus for minimizing skew between signals

Configurable delay circuitry with compensated delay

Digital PVT compensation for delay chain

Write-leveling implementation in programmable logic devices

Duty cycle correction circuit for memory interfaces in integrated c...

High performance memory interface circuit architecture

Multiple data rate interface architecture

Variation compensation circuitry for memory interface

Programmable output buffer

Programmable high-speed interface

Techniques for buffering single-ended and differential signals

Configurable input-output (I/O) circuitry with pre-emphasis circuitry

High-performance memory interface circuit architecture

Techniques for generating PVT compensated phase offset to improve a...

Techniques for providing multiple delay paths in a delay circuit

Techniques for providing reduced duty cycle distortion

Write-leveling implementation in programmable logic devices

Multiple data rate interface architecture

Postamble timing for DDR memories

Read-leveling implementations for DDR3 applications on an FPGA

PVT compensated auto-calibration scheme for DDR3

Patents Applicationslast 30 patents

Programmable High-Speed I/O Interface

Programmable High-Speed I/O Interface

PROGRAMMABLE HIGH-SPEED I/O INTERFACE

MULTIPLE DATA RATE INTERFACE ARCHITECTURE

PROGRAMMABLE HIGH-SPEED I/O INTERFACE

MULTIPLE DATA RATE INTERFACE ARCHITECTURE

WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES

PROGRAMMABLE HIGH-SPEED INTERFACE

METHOD AND APPARATUS FOR MINIMIZING SKEW BETWEEN SIGNALS

DUTY CYCLE CORRECTION CIRCUIT FOR MEMORY INTERFACES IN INTEGRATED C...

Techniques for Providing Reduced Duty Cycle Distortion

PROGRAMMABLE HIGH-SPEED INTERFACE

READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA

READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA

WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES

PROGRAMMABLE HIGH-SPEED INTERFACE

SOFT ERROR LOCATION AND SENSITIVITY DETECTION FOR PROGRAMMABLE DEVICES

Read-Side Calibration for Data Interface

Write-Side Calibration for Data Interface

System and method for deploying an SQL procedure

Supporting multiple versions of a routine

Programmable high speed interface

Loop circuitry with low-pass noise filter

Supply voltage detection circuit

Programmable I/O element circuit for high speed logic devices

Programmable high speed I/O interface

Programmable logic array integrated circuits

Programmable logic array integrated circuit devices

Programmable high speed I/O interface

Programmable logic array integrated circuit devices