Joseph M. McCrate

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Iterative decoder for correcting dram device failures
- Patent number 12,170,531
- Issue date Dec 17, 2024
- Micron Technology, Inc.
- Joseph M. McCrate
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data protection and recovery
- Patent number 12,072,766
- Issue date Aug 27, 2024
- Micron Technology, Inc.
- Marco Sforzin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device architecture using multiple physical cells per bit to...
- Patent number 12,020,743
- Issue date Jun 25, 2024
- Micron Technology, Inc.
- Joseph Michael McCrate
- G11 - INFORMATION STORAGE
Information Patent Grant
Iterative decoding technique for correcting DRAM device failures
- Patent number 11,962,327
- Issue date Apr 16, 2024
- Micron Technology, Inc.
- Joseph M. McCrate
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Error detection and correction in memory
- Patent number 11,868,211
- Issue date Jan 9, 2024
- Micron Technology, Inc.
- Joseph M. McCrate
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory electrodes and formation thereof
- Patent number 11,711,987
- Issue date Jul 25, 2023
- Micron Technology, Inc.
- Joseph M. McCrate
Information Patent Grant
Memory device architecture using multiple physical cells per bit to...
- Patent number 11,605,418
- Issue date Mar 14, 2023
- Micron Technology, Inc.
- Joseph Michael McCrate
- G11 - INFORMATION STORAGE
Information Patent Grant
Error detection and correction in memory
- Patent number 11,455,210
- Issue date Sep 27, 2022
- Micron Technology, Inc.
- Joseph M. McCrate
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for applying multiple voltage pulses to select a memory...
- Patent number 11,367,483
- Issue date Jun 21, 2022
- Micron Technology Inc.
- Josephine T. Hamada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for applying multiple voltage pulses to select a memory...
- Patent number 10,867,671
- Issue date Dec 15, 2020
- Micron Technology, Inc.
- Josephine T. Hamada
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
DATA PROTECTION AND RECOVERY
- Publication number 20240411644
- Publication date Dec 12, 2024
- Micron Technology, Inc.
- Marco Sforzin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ITERATIVE DECODING TECHNIQUE FOR CORRECTING DRAM DEVICE FAILURES
- Publication number 20240413842
- Publication date Dec 12, 2024
- Micron Technology, Inc.
- Joseph M. McCrate
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DECODER FOR INTERLEAVED REED-SOLOMON (IRS) WITH ERASURE/COLLABORATIVE
- Publication number 20240378114
- Publication date Nov 14, 2024
- Micron Technology, Inc.
- Joseph M. MCCRATE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COLLABORATIVE DECODING WITH ERASURE SEARCH TO RECOVER CORNER FAILS
- Publication number 20240378113
- Publication date Nov 14, 2024
- Micron Technology, Inc.
- Joseph M. MCCRATE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DECODER FOR BURST CORRECTION READ SOLOMON DECODING FOR MEMORY APPLI...
- Publication number 20240345920
- Publication date Oct 17, 2024
- Micron Technology, Inc.
- Joseph M. MCCRATE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE ARCHITECTURE USING MULTIPLE PHYSICAL CELLS PER BIT TO...
- Publication number 20240339149
- Publication date Oct 10, 2024
- Micron Technology, Inc.
- Joseph Michael McCrate
- G11 - INFORMATION STORAGE
Information Patent Application
DATA PROTECTION AND RECOVERY
- Publication number 20240303159
- Publication date Sep 12, 2024
- Micron Technology, Inc.
- Joseph M. McCrate
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HETEROGENOUS INTERLEAVED REED-SOLOMON (HETIRS) WITH ERASURE DECODING
- Publication number 20240297668
- Publication date Sep 5, 2024
- Micron Technology, Inc.
- Joseph M. MCCRATE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERLEAVED REED-SOLOMON (IRS) WITH COLLABORATIVE DECODING
- Publication number 20240296090
- Publication date Sep 5, 2024
- Micron Technology, Inc.
- Joseph M. MCCRATE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BURST CORRECTION REED SOLOMON DECODING FOR MEMORY APPLICATIONS
- Publication number 20240272981
- Publication date Aug 15, 2024
- Micron Technology, Inc.
- Joseph M. MCCRATE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PROTECTION AND RECOVERY
- Publication number 20240111629
- Publication date Apr 4, 2024
- Micron Technology, Inc.
- Marco Sforzin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA CORRECTION SCHEME WITH REDUCED DEVICE OVERHEAD
- Publication number 20240004756
- Publication date Jan 4, 2024
- Micron Technology, Inc.
- Joseph M. McCrate
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ITERATIVE DECODING TECHNIQUE FOR CORRECTING DRAM DEVICE FAILURES
- Publication number 20230223960
- Publication date Jul 13, 2023
- Micron Technology, Inc.
- Joseph M. McCrate
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ITERATIVE DECODER FOR CORRECTING DRAM DEVICE FAILURES
- Publication number 20230223961
- Publication date Jul 13, 2023
- Micron Technology, Inc.
- Joseph M. McCrate
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MEMORY DEVICE ARCHITECTURE USING MULTIPLE PHYSICAL CELLS PER BIT TO...
- Publication number 20230215489
- Publication date Jul 6, 2023
- Micron Technology, Inc.
- Joseph Michael McCrate
- G11 - INFORMATION STORAGE
Information Patent Application
ERROR DETECTION AND CORRECTION IN MEMORY
- Publication number 20230014459
- Publication date Jan 19, 2023
- Micron Technology, Inc.
- Joseph M. McCrate
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE ARCHITECTURE USING MULTIPLE CELLS PER BIT
- Publication number 20220130447
- Publication date Apr 28, 2022
- Micron Technology, Inc.
- Joseph Michael McCrate
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ELECTRODES AND FORMATION THEREOF
- Publication number 20220069207
- Publication date Mar 3, 2022
- Micron Technology, Inc.
- Joseph M. McCrate
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELL SELECTION
- Publication number 20210151107
- Publication date May 20, 2021
- Micron Technology, Inc.
- Josephine T. Hamada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR APPLYING MULTIPLE VOLTAGE PULSES TO SELECT A MEMORY...
- Publication number 20210005254
- Publication date Jan 7, 2021
- Micron Technology, Inc.
- Josephine T. Hamada
- G11 - INFORMATION STORAGE

Joseph M. McCrate

Person

Patents Grantslast 30 patents

Iterative decoder for correcting dram device failures

Data protection and recovery

Memory device architecture using multiple physical cells per bit to...

Iterative decoding technique for correcting DRAM device failures

Error detection and correction in memory

Memory electrodes and formation thereof

Memory device architecture using multiple physical cells per bit to...

Error detection and correction in memory

Techniques for applying multiple voltage pulses to select a memory...

Techniques for applying multiple voltage pulses to select a memory...

Patents Applicationslast 30 patents

DATA PROTECTION AND RECOVERY

ITERATIVE DECODING TECHNIQUE FOR CORRECTING DRAM DEVICE FAILURES

DECODER FOR INTERLEAVED REED-SOLOMON (IRS) WITH ERASURE/COLLABORATIVE

COLLABORATIVE DECODING WITH ERASURE SEARCH TO RECOVER CORNER FAILS

DECODER FOR BURST CORRECTION READ SOLOMON DECODING FOR MEMORY APPLI...

MEMORY DEVICE ARCHITECTURE USING MULTIPLE PHYSICAL CELLS PER BIT TO...

DATA PROTECTION AND RECOVERY

HETEROGENOUS INTERLEAVED REED-SOLOMON (HETIRS) WITH ERASURE DECODING

INTERLEAVED REED-SOLOMON (IRS) WITH COLLABORATIVE DECODING

BURST CORRECTION REED SOLOMON DECODING FOR MEMORY APPLICATIONS

DATA PROTECTION AND RECOVERY

DATA CORRECTION SCHEME WITH REDUCED DEVICE OVERHEAD

ITERATIVE DECODING TECHNIQUE FOR CORRECTING DRAM DEVICE FAILURES

ITERATIVE DECODER FOR CORRECTING DRAM DEVICE FAILURES

MEMORY DEVICE ARCHITECTURE USING MULTIPLE PHYSICAL CELLS PER BIT TO...

ERROR DETECTION AND CORRECTION IN MEMORY

MEMORY DEVICE ARCHITECTURE USING MULTIPLE CELLS PER BIT

MEMORY ELECTRODES AND FORMATION THEREOF

MEMORY CELL SELECTION

TECHNIQUES FOR APPLYING MULTIPLE VOLTAGE PULSES TO SELECT A MEMORY...