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Joseph Nahas
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Notre Dame, IN, US
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Patents Grants
last 30 patents
Information
Patent Grant
Systems and methods for filtering and computation using tunneling t...
Patent number
9,825,132
Issue date
Nov 21, 2017
University of Notre Dame Du Lac
Behnam Sedighi
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Devices for utilizing symFETs for low-power information processing
Patent number
9,362,919
Issue date
Jun 7, 2016
University of Notre Dame du Lac
Behnam Sedighi
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Random access memory architecture including midpoint reference
Patent number
8,184,476
Issue date
May 22, 2012
EVERSPIN TECHNOLOGIES, INC.
Joseph J. Nahas
G11 - INFORMATION STORAGE
Information
Patent Grant
Toggle memory burst
Patent number
7,543,211
Issue date
Jun 2, 2009
EVERSPIN TECHNOLOGIES, INC.
Joseph J. Nahas
G11 - INFORMATION STORAGE
Information
Patent Grant
MRAM having error correction code circuitry and method therefor
Patent number
7,370,260
Issue date
May 6, 2008
FREESCALE SEMICONDUCTOR, INC.
Joseph J. Nahas
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Sense amplifier with multiple bits sharing a common reference
Patent number
7,292,484
Issue date
Nov 6, 2007
FREESCALE SEMICONDUCTOR, INC.
Thomas W. Andre
G11 - INFORMATION STORAGE
Information
Patent Grant
MRAM with a write driver and method therefor
Patent number
7,280,388
Issue date
Oct 9, 2007
Joseph J. Nahas
G11 - INFORMATION STORAGE
Information
Patent Grant
Magnetoresistive random access memory simulation
Patent number
7,266,486
Issue date
Sep 4, 2007
FREESCALE SEMICONDUCTOR, INC.
Joseph J. Nahas
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
MRAM memory with residual write field reset
Patent number
7,206,223
Issue date
Apr 17, 2007
FREESCALE SEMICONDUCTOR, INC.
Joseph J. Nahas
G11 - INFORMATION STORAGE
Information
Patent Grant
MRAM architecture with electrically isolated read and write circuitry
Patent number
7,154,772
Issue date
Dec 26, 2006
FREESCALE SEMICONDUCTOR, INC.
Joseph J. Nahas
G11 - INFORMATION STORAGE
Information
Patent Grant
Method and apparatus for simulating a magnetoresistive random acces...
Patent number
7,082,389
Issue date
Jul 25, 2006
FREESCALE SEMICONDUCTOR, INC.
Joseph J. Nahas
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Circuit and method for current pulse compensation
Patent number
7,012,841
Issue date
Mar 14, 2006
FREESCALE SEMICONDUCTOR, INC.
Joseph J. Nahas
G11 - INFORMATION STORAGE
Information
Patent Grant
Magnetoresistive random access memory (MRAM) cell having a diode wi...
Patent number
6,944,052
Issue date
Sep 13, 2005
FREESCALE SEMICONDUCTOR, INC.
Chitra K. Subramanian
G11 - INFORMATION STORAGE
Information
Patent Grant
MRAM and methods for reading the MRAM
Patent number
6,909,631
Issue date
Jun 21, 2005
FREESCALE SEMICONDUCTOR, INC.
Mark A. Durlam
G11 - INFORMATION STORAGE
Information
Patent Grant
MRAM architecture with electrically isolated read and write circuitry
Patent number
6,903,964
Issue date
Jun 7, 2005
FREESCALE SEMICONDUCTOR, INC.
Joseph J. Nahas
G11 - INFORMATION STORAGE
Information
Patent Grant
Accelerated life test of MRAM cells
Patent number
6,894,937
Issue date
May 17, 2005
FREESCALE SEMICONDUCTOR, INC.
Bradley J. Garni
G11 - INFORMATION STORAGE
Information
Patent Grant
MRAM architecture
Patent number
6,888,743
Issue date
May 3, 2005
FREESCALE SEMICONDUCTOR, INC.
Mark A. Durlam
G11 - INFORMATION STORAGE
Information
Patent Grant
Circuit for write field disturbance cancellation in an MRAM and met...
Patent number
6,859,388
Issue date
Feb 22, 2005
FREESCALE SEMICONDUCTOR, INC.
Joseph J. Nahas
G11 - INFORMATION STORAGE
Information
Patent Grant
Write driver for a magnetoresistive memory
Patent number
6,842,365
Issue date
Jan 11, 2005
FREESCALE SEMICONDUCTOR, INC.
Joseph J. Nahas
G11 - INFORMATION STORAGE
Information
Patent Grant
Sense amplifier and method for performing a read operation in a MRAM
Patent number
6,760,266
Issue date
Jul 6, 2004
FREESCALE SEMICONDUCTOR, INC.
Bradley J. Garni
G11 - INFORMATION STORAGE
Information
Patent Grant
Circuit and method for reading a toggle memory cell
Patent number
6,744,663
Issue date
Jun 1, 2004
Motorola, Inc.
Brad J. Garni
G11 - INFORMATION STORAGE
Information
Patent Grant
MRAM architecture with a grounded write bit line and electrically i...
Patent number
6,714,442
Issue date
Mar 30, 2004
Motorola, Inc.
Joseph J. Nahas
G11 - INFORMATION STORAGE
Information
Patent Grant
Memory architecture with write circuitry and method therefor
Patent number
6,714,440
Issue date
Mar 30, 2004
Motorola, Inc.
Chitra K. Subramanian
G11 - INFORMATION STORAGE
Information
Patent Grant
Balanced load memory and method of operation
Patent number
6,711,068
Issue date
Mar 23, 2004
Motorola, Inc.
Chitra K. Subramanian
G11 - INFORMATION STORAGE
Information
Patent Grant
Memory having a precharge circuit and method therefor
Patent number
6,711,052
Issue date
Mar 23, 2004
Motorola, Inc.
Chitra K. Subramanian
G11 - INFORMATION STORAGE
Information
Patent Grant
Sense amplifier bias circuit for a memory having at least two disti...
Patent number
6,700,814
Issue date
Mar 2, 2004
Motorola, Inc.
Joseph J. Nahas
G11 - INFORMATION STORAGE
Information
Patent Grant
Circuit and method of writing a toggle memory
Patent number
6,693,824
Issue date
Feb 17, 2004
Motorola, Inc.
Joseph J. Nahas
G11 - INFORMATION STORAGE
Information
Patent Grant
Magnetic memory and method of bi-directional write current programming
Patent number
6,667,899
Issue date
Dec 23, 2003
Motorola, Inc.
Chitra K. Subramanian
G11 - INFORMATION STORAGE
Information
Patent Grant
Memory having write current ramp rate control
Patent number
6,657,889
Issue date
Dec 2, 2003
Motorola, Inc.
Chitra K. Subramanian
G11 - INFORMATION STORAGE
Information
Patent Grant
Sense amplifier incorporating a symmetric midpoint reference
Patent number
6,621,729
Issue date
Sep 16, 2003
Motorola, Inc.
Bradley J. Garni
G11 - INFORMATION STORAGE
Patents Applications
last 30 patents
Information
Patent Application
SYSTEMS AND METHODS FOR FILTERING AND COMPUTATION USING TUNNELLING...
Publication number
20170103979
Publication date
Apr 13, 2017
UNIVERSITY OF NOTRE DAME DU LAC
Behnam Sedighi
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Application
DEVICES FOR UTILIZING SYMFETS FOR LOW-POWER INFORMATION PROCESSING
Publication number
20160182055
Publication date
Jun 23, 2016
UNIVERSITY OF NOTRE DAME DU LAC
Behnam Sedighi
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Application
Random access memory architecture including midpoint reference
Publication number
20100165710
Publication date
Jul 1, 2010
EVERSPIN TECHNOLOGIES, INC.
Joseph J. NAHAS
G11 - INFORMATION STORAGE
Information
Patent Application
MRAM WITH A WRITE DRIVER AND A METHOD THEREFOR
Publication number
20070291531
Publication date
Dec 20, 2007
FREESCALE SEMICONDUCTOR, INC.
Joseph J. Nahas
G11 - INFORMATION STORAGE
Information
Patent Application
MRAM ARRAY WITH REFERENCE CELL ROW AND METHOF OF OPERATION
Publication number
20070247939
Publication date
Oct 25, 2007
Joseph J. Nahas
G11 - INFORMATION STORAGE
Information
Patent Application
MRAM with a write driver and method therefor
Publication number
20070133262
Publication date
Jun 14, 2007
Joseph J. Nahas
G11 - INFORMATION STORAGE
Information
Patent Application
Toggle memory burst
Publication number
20060174172
Publication date
Aug 3, 2006
Joseph J. Nahas
G11 - INFORMATION STORAGE
Information
Patent Application
CIRCUIT AND METHOD FOR CURRENT PULSE COMPENSATION
Publication number
20060044882
Publication date
Mar 2, 2006
Joseph J. Nahas
G11 - INFORMATION STORAGE
Information
Patent Application
Magnetoresistive random access memory simulation
Publication number
20050216244
Publication date
Sep 29, 2005
Joseph J. Nahas
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
MRAM architecture with electrically isolated read and write circuitry
Publication number
20050152183
Publication date
Jul 14, 2005
Joseph J. Nahas
G11 - INFORMATION STORAGE
Information
Patent Application
MRAM having error correction code circuitry and method therefor
Publication number
20050144551
Publication date
Jun 30, 2005
Joseph J. Nahas
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Magnetoresistive random access memory (MRAM) cell having a diode wi...
Publication number
20050083760
Publication date
Apr 21, 2005
Chitra K. Subramanian
G11 - INFORMATION STORAGE
Information
Patent Application
ACCELERATED LIFE TEST OF MRAM CELLS
Publication number
20050068815
Publication date
Mar 31, 2005
Bradley J. Garni
G11 - INFORMATION STORAGE
Information
Patent Application
CIRCUIT FOR WRITE FIELD DISTURBANCE CANCELLATION IN AN MRAM AND MET...
Publication number
20050052901
Publication date
Mar 10, 2005
Joseph J. Nahas
G11 - INFORMATION STORAGE
Information
Patent Application
MRAM and methods for reading the MRAM
Publication number
20040125649
Publication date
Jul 1, 2004
Mark A. Durlam
G11 - INFORMATION STORAGE
Information
Patent Application
MRAM architecture
Publication number
20040125646
Publication date
Jul 1, 2004
Mark A. Durlam
G11 - INFORMATION STORAGE
Information
Patent Application
Magnetoresistive random access memory (MRAM) cell having a diode wi...
Publication number
20040100817
Publication date
May 27, 2004
Chitra K. Subramanian
G11 - INFORMATION STORAGE
Information
Patent Application
Method and apparatus for simulating a magnetoresistive random acces...
Publication number
20040102943
Publication date
May 27, 2004
Joseph J. Nahas
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Circuit and method for reading a toggle memory cell
Publication number
20040008536
Publication date
Jan 15, 2004
Bradley J. Garni
G11 - INFORMATION STORAGE
Information
Patent Application
Sense amplifier and method for performing a read operation in a MRAM
Publication number
20040001383
Publication date
Jan 1, 2004
Bradley J. Garni
G11 - INFORMATION STORAGE
Information
Patent Application
Memory having a precharge circuit and method therefor
Publication number
20040001351
Publication date
Jan 1, 2004
Chitra K. Subramanian
G11 - INFORMATION STORAGE
Information
Patent Application
BALANCED LOAD MEMORY AND METHOD OF OPERATION
Publication number
20040001361
Publication date
Jan 1, 2004
Chitra K. Subramanian
G11 - INFORMATION STORAGE
Information
Patent Application
MRAM architecture with electrically isolated read and write circuitry
Publication number
20040001358
Publication date
Jan 1, 2004
Joseph J. Nahas
G11 - INFORMATION STORAGE
Information
Patent Application
CIRCUIT AND METHOD OF WRITING A TOGGLE MEMORY
Publication number
20040001352
Publication date
Jan 1, 2004
Joseph J. Nahas
G11 - INFORMATION STORAGE
Information
Patent Application
Memory architecture with write circuitry and method therefor
Publication number
20040001360
Publication date
Jan 1, 2004
Chitra K. Subramanian
G11 - INFORMATION STORAGE