Joseph P. GERGEN

Person

Manchaca, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Hardware-based memory management for system-on-chip (SoC) integrate...
- Patent number 10,817,413
- Issue date Oct 27, 2020
- NXP USA, INC.
- Kaushik Arvind
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for controlling wake events in a data processi...
- Patent number 9,900,390
- Issue date Feb 20, 2018
- NXP USA, INC.
- David C. Holloway
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Explicit barrier scheduling mechanism for pipelining of stream proc...
- Patent number 9,207,979
- Issue date Dec 8, 2015
- FREESCALE SEMICONDUCTOR, INC.
- James C. Holt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Event triggered memory mapped access
- Patent number 8,700,878
- Issue date Apr 15, 2014
- FREESCALE SEMICONDUCTOR, INC.
- William D. Schwarz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase locked loop device and method thereof
- Patent number 8,509,370
- Issue date Aug 13, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Gayathri A. Bhagavatheeswaran
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for debugging a data processing system
- Patent number 7,107,489
- Issue date Sep 12, 2006
- FREESCALE SEMICONDUCTOR, INC.
- Joseph P. Gergen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for debugging a data processing system
- Patent number 7,013,409
- Issue date Mar 14, 2006
- FREESCALE SEMICONDUCTOR, INC.
- Joseph P. Gergen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single instruction for multiple loops
- Patent number 6,842,895
- Issue date Jan 11, 2005
- FREESCALE SEMICONDUCTOR, INC.
- Pascal L. Renard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for pipeline hazard detection
- Patent number 6,751,759
- Issue date Jun 15, 2004
- FREESCALE SEMICONDUCTOR, INC.
- Xiao Sun
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Hardware-Based Memory Management For System-On-Chip (SOC) Integrate...
- Publication number 20200183823
- Publication date Jun 11, 2020
- NXP USA, Inc.
- Kaushik Arvind
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CONTROLLING WAKE EVENTS IN A DATA PROCESSI...
- Publication number 20160344820
- Publication date Nov 24, 2016
- FREESCALE SEMICONDUCTOR, INC.
- David C. HOLLOWAY
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
EXPLICIT BARRIER SCHEDULING MECHANISM FOR PIPELINING OF STREAM PROC...
- Publication number 20150347185
- Publication date Dec 3, 2015
- FREESCALE SEMICONDUCTOR, INC.
- James C. Holt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Event Triggered Memory Mapped Access
- Publication number 20100318752
- Publication date Dec 16, 2010
- FREESCALE SEMICONDUCTOR, INC.
- William D. Schwarz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHASE LOCKED LOOP DEVICE AND METHOD THEREOF
- Publication number 20100310030
- Publication date Dec 9, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Gayathri A. Bhagavatheeswaran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus for debugging a data processing system
- Publication number 20040019825
- Publication date Jan 29, 2004
- Joseph P. Gergen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for debugging a data processing system
- Publication number 20040019828
- Publication date Jan 29, 2004
- Joseph P. Gergen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for debugging a data processing system
- Publication number 20040019831
- Publication date Jan 29, 2004
- Joseph P. Gergen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Single instruction for multiple loops
- Publication number 20020083305
- Publication date Jun 27, 2002
- Pascal L. Renard
- G06 - COMPUTING CALCULATING COUNTING

Joseph P. GERGEN

Person

Patents Grantslast 30 patents

Hardware-based memory management for system-on-chip (SoC) integrate...

Method and apparatus for controlling wake events in a data processi...

Explicit barrier scheduling mechanism for pipelining of stream proc...

Event triggered memory mapped access

Phase locked loop device and method thereof

Method and apparatus for debugging a data processing system

Method and apparatus for debugging a data processing system

Single instruction for multiple loops

Method and apparatus for pipeline hazard detection

Patents Applicationslast 30 patents

Hardware-Based Memory Management For System-On-Chip (SOC) Integrate...

METHOD AND APPARATUS FOR CONTROLLING WAKE EVENTS IN A DATA PROCESSI...

EXPLICIT BARRIER SCHEDULING MECHANISM FOR PIPELINING OF STREAM PROC...

Event Triggered Memory Mapped Access

PHASE LOCKED LOOP DEVICE AND METHOD THEREOF

Method and apparatus for debugging a data processing system

Method and apparatus for debugging a data processing system

Method and apparatus for debugging a data processing system

Single instruction for multiple loops