Joseph R. Wright

Person

Round Rock, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
System on a chip (SoC) having a low power mode of operation
- Patent number 12,306,652
- Issue date May 20, 2025
- NXP USA, INC.
- Vivek Kumar Yadav
- G05 - CONTROLLING REGULATING
Information Patent Grant
System and method for facilitating built-in self-test of system-on-...
- Patent number 11,513,153
- Issue date Nov 29, 2022
- NXP USA, INC.
- Rohan Poudel
- G01 - MEASURING TESTING
Information Patent Grant
Low power mode testing in an integrated circuit
- Patent number 11,047,904
- Issue date Jun 29, 2021
- NXP USA, INC.
- Kumar Abhishek
- G01 - MEASURING TESTING
Information Patent Grant
Correctable error filtering for input/output subsystem
- Patent number 10,078,543
- Issue date Sep 18, 2018
- Oracle International Corporation
- John E. Watkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address space expander for a processor
- Patent number 9,990,282
- Issue date Jun 5, 2018
- Oracle International Corporation
- Joseph Wright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Congestion management in distributed systems using autonomous self-...
- Patent number 9,985,891
- Issue date May 29, 2018
- Oracle International Corporation
- John Watkins
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Ring controller for PCIe message handling
- Patent number 9,806,904
- Issue date Oct 31, 2017
- Oracle International Corporation
- John E. Watkins
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
FAULT INTERFACE ARCHITECTURE IN SAFETY-RELEVANT SYSTEMS
- Publication number 20250156261
- Publication date May 15, 2025
- NXP USA, Inc.
- Kumar Abhishek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM ON A CHIP (SOC) HAVING A LOW POWER MODE OF OPERATION
- Publication number 20250123648
- Publication date Apr 17, 2025
- NXP USA, Inc.
- Vivek Kumar Yadav
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR FACILITATING BUILT-IN SELF-TEST OF SYSTEM-ON-...
- Publication number 20220334181
- Publication date Oct 20, 2022
- NXP USA, Inc.
- Rohan Poudel
- G01 - MEASURING TESTING
Information Patent Application
LOW POWER MODE TESTING IN AN INTEGRATED CIRCUIT
- Publication number 20200284830
- Publication date Sep 10, 2020
- NXP USA, Inc.
- Kumar ABHISHEK
- G01 - MEASURING TESTING
Information Patent Application
Correctable Error Filtering for Input/Output Subsystem
- Publication number 20170344419
- Publication date Nov 30, 2017
- Oracle International Corporation
- John E. Watkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Address Space Expander for a Processor
- Publication number 20170315912
- Publication date Nov 2, 2017
- Oracle International Corporation
- Joseph Wright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Congestion Management in Distributed Systems Using Autonomous Self-...
- Publication number 20170295098
- Publication date Oct 12, 2017
- Oracle International Corporation
- John Watkins
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Ring Controller for PCIe Message Handling
- Publication number 20170070363
- Publication date Mar 9, 2017
- Oracle International Corporation
- John E. Watkins
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Joseph R. Wright

Person

Patents Grantslast 30 patents

System on a chip (SoC) having a low power mode of operation

System and method for facilitating built-in self-test of system-on-...

Low power mode testing in an integrated circuit

Correctable error filtering for input/output subsystem

Address space expander for a processor

Congestion management in distributed systems using autonomous self-...

Ring controller for PCIe message handling

Patents Applicationslast 30 patents

FAULT INTERFACE ARCHITECTURE IN SAFETY-RELEVANT SYSTEMS

SYSTEM ON A CHIP (SOC) HAVING A LOW POWER MODE OF OPERATION

SYSTEM AND METHOD FOR FACILITATING BUILT-IN SELF-TEST OF SYSTEM-ON-...

LOW POWER MODE TESTING IN AN INTEGRATED CIRCUIT

Correctable Error Filtering for Input/Output Subsystem

Address Space Expander for a Processor

Congestion Management in Distributed Systems Using Autonomous Self-...

Ring Controller for PCIe Message Handling