Joseph Skrovan

Person

Buda, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Internal self-test circuit for a memory array
- Patent number 6,785,856
- Issue date Aug 31, 2004
- Advanced Micro Devices, Inc.
- Allan Parker
- G11 - INFORMATION STORAGE
Information Patent Grant
Interlaced multi-level memory
- Patent number 6,707,713
- Issue date Mar 16, 2004
- Advanced Micro Devices, Inc.
- Allan Parker
- G11 - INFORMATION STORAGE
Information Patent Grant
Reliability monitor for a memory array
- Patent number 6,684,353
- Issue date Jan 27, 2004
- Advanced Micro Devices, Inc.
- Allan Parker
- G11 - INFORMATION STORAGE
Information Patent Grant
User selectable cell programming
- Patent number 6,424,569
- Issue date Jul 23, 2002
- Advanced Micro Devices, Inc.
- Allan Parker
- G11 - INFORMATION STORAGE
Information Patent Grant
Configure registers and loads to tailor a multi-level cell flash de...
- Patent number 6,400,624
- Issue date Jun 4, 2002
- Advanced Micro Devices, Inc.
- Allan Parker
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for generating functional tests for a microprocessor having...
- Patent number 6,112,312
- Issue date Aug 29, 2000
- Advanced Micro Devices, Inc.
- Allan Parker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Program/verify technique for multi-level flash cells enabling diffe...
- Patent number 6,091,631
- Issue date Jul 18, 2000
- Advanced Micro Devices, Inc.
- Joe Kucera
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for event-related functional testing of a microprocessor
- Patent number 6,016,554
- Issue date Jan 18, 2000
- Advanced Micro Devices, Inc.
- Joseph C. Skrovan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherency test system and methodology for testing cache opera...
- Patent number 5,960,457
- Issue date Sep 28, 1999
- Advanced Micro Devices, Inc.
- Joseph Skrovan
- G06 - COMPUTING CALCULATING COUNTING

Joseph Skrovan

Person

Patents Grantslast 30 patents

Internal self-test circuit for a memory array

Interlaced multi-level memory

Reliability monitor for a memory array

User selectable cell programming

Configure registers and loads to tailor a multi-level cell flash de...

Method for generating functional tests for a microprocessor having...

Program/verify technique for multi-level flash cells enabling diffe...

Method for event-related functional testing of a microprocessor

Cache coherency test system and methodology for testing cache opera...