Joseph W. Cowan

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West Linn, OR, US

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Patents Grantslast 30 patents

Information Patent Grant
Method of mapping logic failures in an integrated circuit die
- Patent number 6,986,112
- Issue date Jan 10, 2006
- LSI Logic Corporation
- Bruce Whitefield
- G01 - MEASURING TESTING
Information Patent Grant
Simulated voltage contrasted image generator and comparator
- Patent number 6,951,000
- Issue date Sep 27, 2005
- LSI Logic Corporation
- Joseph Cowan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of translating a net description of an integrated circuit die
- Patent number 6,865,435
- Issue date Mar 8, 2005
- LSI Logic Corporation
- Joseph Cowan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Grounding mechanism for semiconductor devices
- Patent number 6,864,563
- Issue date Mar 8, 2005
- LSI Logic Corporation
- Joseph W. Cowan
- G01 - MEASURING TESTING
Information Patent Grant
Net segment analyzer for chip CAD layout
- Patent number 6,817,004
- Issue date Nov 9, 2004
- LSI Logic Corporation
- Joseph W. Cowan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device under interface card with on-board testing
- Patent number 6,747,473
- Issue date Jun 8, 2004
- LSI Logic Corporation
- Joseph W. Cowan
- G01 - MEASURING TESTING
Information Patent Grant
Interconnector and method of connecting probes to a die for functio...
- Patent number 6,605,951
- Issue date Aug 12, 2003
- LSI Logic Corporation
- Joseph W. Cowan
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF TRANSLATING A NET DESCRIPTION OF AN INTEGRATED CIRCUIT DIE
- Publication number 20050055656
- Publication date Mar 10, 2005
- Joseph Cowan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of mapping logic failures in an integrated circuit die
- Publication number 20050028115
- Publication date Feb 3, 2005
- Bruce Whitefield
- G01 - MEASURING TESTING
Information Patent Application
Net segment analyzer for chip CAD layout
- Publication number 20040143809
- Publication date Jul 22, 2004
- Joseph W. Cowan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Simulated voltage contrast image generator and comparator
- Publication number 20040143803
- Publication date Jul 22, 2004
- Joseph Cowan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Device under test interface card with on-board testing
- Publication number 20040059971
- Publication date Mar 25, 2004
- LSI Logic Corporation
- Joseph W. Cowan
- G01 - MEASURING TESTING