Juhan Kim

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method, apparatus and system for wide metal line for SADP routing
- Patent number 11,205,033
- Issue date Dec 21, 2021
- GLOBALFOUNDRIES Inc.
- Lei Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus and system for wide metal line for SADP routing
- Patent number 10,846,452
- Issue date Nov 24, 2020
- GLOBALFOUNDRIES Inc.
- Lei Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
CMOS-based integrated circuit products with isolated P-wells for bo...
- Patent number 10,777,558
- Issue date Sep 15, 2020
- GLOBALFOUNDRIES Inc.
- Juhan Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for flexible power staple insertion
- Patent number 10,658,294
- Issue date May 19, 2020
- GLOBALFOUNDRIES Inc.
- Juhan Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure and method for flexible power staple insertion
- Patent number 10,366,954
- Issue date Jul 30, 2019
- GLOBALFOUNDRIES Inc.
- Juhan Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Context aware processing to resolve strong spacing effects due to s...
- Patent number 10,360,334
- Issue date Jul 23, 2019
- GLOBALFOUNDRIES Inc.
- Navneet Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus, and system for improved memory cell design havin...
- Patent number 10,340,288
- Issue date Jul 2, 2019
- GLOBALFOUNDRIES Inc.
- Juhan Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method, apparatus, and system for offset metal power rail for cell...
- Patent number 10,290,582
- Issue date May 14, 2019
- GLOBALFOUNDRIES Inc.
- Lei Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Special construct for continuous non-uniform active region FinFET s...
- Patent number 10,199,378
- Issue date Feb 5, 2019
- GLOBALFOUNDRIES Inc.
- Navneet Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method, apparatus and system for forming recolorable standard cells...
- Patent number 10,108,771
- Issue date Oct 23, 2018
- GLOBALFOUNDRIES Inc.
- Juhan Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Antenna diode circuit for manufacturing of semiconductor devices
- Patent number 10,096,595
- Issue date Oct 9, 2018
- GLOBALFOUNDRIES Inc.
- Juhan Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Special construct for continuous non-uniform active region FinFET s...
- Patent number 9,893,063
- Issue date Feb 13, 2018
- GLOBALFOUNDRIES Inc.
- Navneet Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method, apparatus, and system for offset metal power rail for cell...
- Patent number 9,639,650
- Issue date May 2, 2017
- GLOBALFOUNDRIES Inc.
- Lei Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Special construct for continuous non-uniform RX FinFET standard cells
- Patent number 9,634,003
- Issue date Apr 25, 2017
- GLOBALFOUNDRIES Inc.
- Navneet Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wide pin for improved circuit routing
- Patent number 9,536,035
- Issue date Jan 3, 2017
- GLOBALFOUNDRIES Inc.
- Lei Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory bit cell for reduced layout area
- Patent number 9,530,780
- Issue date Dec 27, 2016
- GLOBALFOUNDRIES Inc.
- Juhan Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory bit cell for reduced layout area
- Patent number 9,391,080
- Issue date Jul 12, 2016
- GLOBALFOUNDRIES Inc.
- Juhan Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Special constructs for continuous non-uniform active region FinFET...
- Patent number 9,337,099
- Issue date May 10, 2016
- GLOBALFOUNDRIES Inc.
- Navneet Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wide pin for improved circuit routing
- Patent number 9,122,830
- Issue date Sep 1, 2015
- GLOBALFOUNDRIES Inc.
- Lei Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit cell with double patterned metal layer structures
- Patent number 9,105,643
- Issue date Aug 11, 2015
- GLOBALFOUNDRIES Inc.
- Juhan Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cross-coupling based design using diffusion contact structures
- Patent number 8,987,128
- Issue date Mar 24, 2015
- GLOBALFOUNDRIES Inc.
- Mahbub Rashed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Densely packed standard cells for integrated circuit products, and...
- Patent number 8,975,712
- Issue date Mar 10, 2015
- GLOBALFOUNDRIES Inc.
- Mahbub Rashed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnection designs using sidewall image transfer (SIT)
- Patent number 8,962,483
- Issue date Feb 24, 2015
- GLOBALFOUNDRIES Inc.
- Youngtag Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FinFET device and methods of fabrication
- Patent number 8,916,441
- Issue date Dec 23, 2014
- GLOBALFOUNDRIES Inc.
- Mahbub Rashed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for improving double patterning route efficiency
- Patent number 8,881,083
- Issue date Nov 4, 2014
- GLOBALFOUNDRIES Inc.
- Yunfei Deng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit cell with double patterned metal layer structures
- Patent number 8,823,178
- Issue date Sep 2, 2014
- GLOBALFOUNDRIES Inc.
- Juhan Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bit cell with triple patterned metal layer structures
- Patent number 8,791,577
- Issue date Jul 29, 2014
- GLOBALFOUNDRIES Inc.
- Juhan Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High speed FRAM including a deselect circuit
- Patent number 8,072,790
- Issue date Dec 6, 2011
- Juhan Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Very high speed FRAM for replacing SRAM
- Patent number 8,064,242
- Issue date Nov 22, 2011
- Juhan Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
DRAM including pseudo negative word line
- Patent number 7,990,755
- Issue date Aug 2, 2011
- Juhan Kim
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR WIDE METAL LINE FOR SADP ROUTING
- Publication number 20210027005
- Publication date Jan 28, 2021
- GLOBALFOUNDRIES INC.
- Lei Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CMOS-BASED INTEGRATED CIRCUIT PRODUCTS WITH ISOLATED P-WELLS FOR BO...
- Publication number 20200295004
- Publication date Sep 17, 2020
- GLOBALFOUNDRIES INC.
- Juhan Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD FOR FLEXIBLE POWER STAPLE INSERTION
- Publication number 20190333853
- Publication date Oct 31, 2019
- GLOBALFOUNDRIES INC.
- Juhan Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTEXT AWARE PROCESSING TO RESOLVE STRONG SPACING EFFECTS DUE TO S...
- Publication number 20180225406
- Publication date Aug 9, 2018
- GLOBALFOUNDRIES INC.
- Navneet Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM ACTIVE REGION FINFET S...
- Publication number 20180122804
- Publication date May 3, 2018
- GLOBALFOUNDRIES INC.
- Navneet JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD, APPARATUS, AND SYSTEM FOR IMPROVED MEMORY CELL DESIGN HAVIN...
- Publication number 20180040631
- Publication date Feb 8, 2018
- GLOBALFOUNDRIES INC.
- Juhan Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR WIDE METAL LINE FOR SADP ROUTING
- Publication number 20180004883
- Publication date Jan 4, 2018
- GLOBALFOUNDRIES INC.
- Lei Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR FORMING RECOLORABLE STANDARD CELLS...
- Publication number 20170316140
- Publication date Nov 2, 2017
- GLOBALFOUNDRIES Inc.
- Juhan Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS, AND SYSTEM FOR OFFSET METAL POWER RAIL FOR CELL...
- Publication number 20170207165
- Publication date Jul 20, 2017
- GLOBALFOUNDRIES INC.
- Lei Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM ACTIVE REGION FINFET S...
- Publication number 20170141109
- Publication date May 18, 2017
- GLOBALFOUNDRIES INC.
- Navneet JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ANTENNA DIODE CIRCUIT FOR MANUFACTURING OF SEMICONDUCTOR DEVICES
- Publication number 20170125403
- Publication date May 4, 2017
- GLOBALFOUNDRIES INC.
- Juhan Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS, AND SYSTEM FOR OFFSET METAL POWER RAIL FOR CELL...
- Publication number 20160342726
- Publication date Nov 24, 2016
- GLOBALFOUNDRIES INC.
- Lei Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY BIT CELL FOR REDUCED LAYOUT AREA
- Publication number 20160322367
- Publication date Nov 3, 2016
- GLOBALFOUNDRIES INC.
- Juhan Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM RX FINFET STANDARD CELLS
- Publication number 20160225763
- Publication date Aug 4, 2016
- GLOBALFOUNDRIES INC.
- Navneet JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WIDE PIN FOR IMPROVED CIRCUIT ROUTING
- Publication number 20150331988
- Publication date Nov 19, 2015
- GLOBALFOUNDRIES INC.
- Lei Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FORMING GATE TIE BETWEEN ABUTTING CELLS AND RESULTING DEVICE
- Publication number 20150311122
- Publication date Oct 29, 2015
- GLOBALFOUNDRIES INC.
- Mahbub RASHED
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WIDE PIN FOR IMPROVED CIRCUIT ROUTING
- Publication number 20140353842
- Publication date Dec 4, 2014
- Lei Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DENSELY PACKED STANDARD CELLS FOR INTEGRATED CIRCUIT PRODUCTS, AND...
- Publication number 20140339647
- Publication date Nov 20, 2014
- GLOBALFOUNDRIES INC.
- Mahbub Rashed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FINFET DEVICE AND METHOD OF FABRICATION
- Publication number 20140339610
- Publication date Nov 20, 2014
- GLOBALFOUNDRIES INC.
- Mahbub Rashed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BIT CELL WITH DOUBLE PATTERENED METAL LAYER STRUCTURES
- Publication number 20140332967
- Publication date Nov 13, 2014
- Juhan KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR IMPROVING DOUBLE PATTERNING ROUTE EFFICIENCY
- Publication number 20140327146
- Publication date Nov 6, 2014
- GLOBALFOUNDRIES INC.
- Yunfei Deng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECTION DESIGNS USING SIDEWALL IMAGE TRANSFER (SIT)
- Publication number 20140273474
- Publication date Sep 18, 2014
- GLOBALFOUNDRIES INC.
- Youngtag WOO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BIT CELL WITH DOUBLE PATTERNED METAL LAYER STRUCTURES
- Publication number 20140077380
- Publication date Mar 20, 2014
- GLOBALFOUNDRIES INC.
- Juhan Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BIT CELL WITH TRIPLE PATTERNED METAL LAYER STRUCTURES
- Publication number 20140077384
- Publication date Mar 20, 2014
- Juhan Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CROSS-COUPLING BASED DESIGN USING DIFFUSION CONTACT STRUCTURES
- Publication number 20140027918
- Publication date Jan 30, 2014
- GLOBALFOUNDRIES INC.
- Mahbub Rashed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High speed FRAM
- Publication number 20120155145
- Publication date Jun 21, 2012
- Juhan Kim
- G11 - INFORMATION STORAGE
Information Patent Application
High speed FRAM including a deselect circuit
- Publication number 20110188287
- Publication date Aug 4, 2011
- Juhan Kim
- G11 - INFORMATION STORAGE
Information Patent Application
DRAM including pseudo negative word line
- Publication number 20100254179
- Publication date Oct 7, 2010
- Juhan Kim
- G11 - INFORMATION STORAGE
Information Patent Application
Flash memory with two-stage sensing scheme
- Publication number 20100182846
- Publication date Jul 22, 2010
- Juhan Kim
- G11 - INFORMATION STORAGE
Information Patent Application
High speed carbon nanotube memory
- Publication number 20100149895
- Publication date Jun 17, 2010
- Juhan Kim
- G11 - INFORMATION STORAGE

Person

Patents Grantslast 30 patents

Method, apparatus and system for wide metal line for SADP routing

Method, apparatus and system for wide metal line for SADP routing

CMOS-based integrated circuit products with isolated P-wells for bo...

Structure and method for flexible power staple insertion

Structure and method for flexible power staple insertion

Context aware processing to resolve strong spacing effects due to s...

Method, apparatus, and system for improved memory cell design havin...

Method, apparatus, and system for offset metal power rail for cell...

Special construct for continuous non-uniform active region FinFET s...

Method, apparatus and system for forming recolorable standard cells...

Antenna diode circuit for manufacturing of semiconductor devices

Special construct for continuous non-uniform active region FinFET s...

Method, apparatus, and system for offset metal power rail for cell...

Special construct for continuous non-uniform RX FinFET standard cells

Wide pin for improved circuit routing

Memory bit cell for reduced layout area

Memory bit cell for reduced layout area

Special constructs for continuous non-uniform active region FinFET...

Wide pin for improved circuit routing

Bit cell with double patterned metal layer structures

Cross-coupling based design using diffusion contact structures

Densely packed standard cells for integrated circuit products, and...

Interconnection designs using sidewall image transfer (SIT)

FinFET device and methods of fabrication

Methods for improving double patterning route efficiency

Bit cell with double patterned metal layer structures

Bit cell with triple patterned metal layer structures

High speed FRAM including a deselect circuit

Very high speed FRAM for replacing SRAM

DRAM including pseudo negative word line

Patents Applicationslast 30 patents

METHOD, APPARATUS AND SYSTEM FOR WIDE METAL LINE FOR SADP ROUTING

CMOS-BASED INTEGRATED CIRCUIT PRODUCTS WITH ISOLATED P-WELLS FOR BO...

STRUCTURE AND METHOD FOR FLEXIBLE POWER STAPLE INSERTION

CONTEXT AWARE PROCESSING TO RESOLVE STRONG SPACING EFFECTS DUE TO S...

SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM ACTIVE REGION FINFET S...

METHOD, APPARATUS, AND SYSTEM FOR IMPROVED MEMORY CELL DESIGN HAVIN...

METHOD, APPARATUS AND SYSTEM FOR WIDE METAL LINE FOR SADP ROUTING

METHOD, APPARATUS AND SYSTEM FOR FORMING RECOLORABLE STANDARD CELLS...

METHOD, APPARATUS, AND SYSTEM FOR OFFSET METAL POWER RAIL FOR CELL...

SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM ACTIVE REGION FINFET S...

ANTENNA DIODE CIRCUIT FOR MANUFACTURING OF SEMICONDUCTOR DEVICES

METHOD, APPARATUS, AND SYSTEM FOR OFFSET METAL POWER RAIL FOR CELL...

MEMORY BIT CELL FOR REDUCED LAYOUT AREA

SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM RX FINFET STANDARD CELLS

WIDE PIN FOR IMPROVED CIRCUIT ROUTING

FORMING GATE TIE BETWEEN ABUTTING CELLS AND RESULTING DEVICE

WIDE PIN FOR IMPROVED CIRCUIT ROUTING

DENSELY PACKED STANDARD CELLS FOR INTEGRATED CIRCUIT PRODUCTS, AND...

FINFET DEVICE AND METHOD OF FABRICATION

BIT CELL WITH DOUBLE PATTERENED METAL LAYER STRUCTURES

METHODS FOR IMPROVING DOUBLE PATTERNING ROUTE EFFICIENCY

INTERCONNECTION DESIGNS USING SIDEWALL IMAGE TRANSFER (SIT)

BIT CELL WITH DOUBLE PATTERNED METAL LAYER STRUCTURES

BIT CELL WITH TRIPLE PATTERNED METAL LAYER STRUCTURES

CROSS-COUPLING BASED DESIGN USING DIFFUSION CONTACT STRUCTURES

High speed FRAM

High speed FRAM including a deselect circuit

DRAM including pseudo negative word line

Flash memory with two-stage sensing scheme

High speed carbon nanotube memory