Jui-Ming Chang

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Method for analyzing path delays in an IC clock tree
- Patent number 6,981,233
- Issue date Dec 27, 2005
- Cadence Design Systems, Inc.
- Jui-Ming Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock tree synthesis for mixed domain clocks
- Patent number 6,782,519
- Issue date Aug 24, 2004
- Cadence Design Systems, Inc.
- Jui-Ming Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock tree synthesizer for balancing reconvergent and crossover clo...
- Patent number 6,763,513
- Issue date Jul 13, 2004
- Cadence Design Systems, Inc.
- Jui-Ming Chang
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
3D MEMORY CELLS AND ARRAY ARCHITECTURES
- Publication number 20240265969
- Publication date Aug 8, 2024
- NEO Semiconductor, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Application
Method for analyzing path delays in an IC clock tree
- Publication number 20040168140
- Publication date Aug 26, 2004
- Jui-Ming Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock tree synthesis for mixed domain clocks
- Publication number 20030182634
- Publication date Sep 25, 2003
- Jui-Ming Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Gated clock tree synthesis
- Publication number 20030135836
- Publication date Jul 17, 2003
- Jui-Ming Chang
- G06 - COMPUTING CALCULATING COUNTING