Jun Pin Tan

Person

Selangor, MY

People

Patents Grantslast 30 patents

Information Patent Grant
Non-destructive readback and writeback for integrated circuit device
- Patent number 12,086,460
- Issue date Sep 10, 2024
- Intel Corporation
- Bee Yee Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable integrated circuit with stacked memory die for storing...
- Patent number 11,487,445
- Issue date Nov 1, 2022
- Intel Corporation
- Aravind Dasu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configuration or data caching for programmable logic device
- Patent number 11,334,263
- Issue date May 17, 2022
- Intel Corporation
- Scott J. Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sector-aligned memory accessible to programmable logic fabric of pr...
- Patent number 11,257,526
- Issue date Feb 22, 2022
- Intel Corporation
- Scott J. Weber
- G11 - INFORMATION STORAGE
Information Patent Grant
Interface for parallel configuration of programmable devices
- Patent number 11,223,361
- Issue date Jan 11, 2022
- Intel Corporation
- Kevin Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatus for accessing configurable memory during hard...
- Patent number 11,086,788
- Issue date Aug 10, 2021
- Intel Corporation
- Jun Pin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface for parallel configuration of programmable devices
- Patent number 10,666,265
- Issue date May 26, 2020
- Intel Corporation
- Kevin Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Criticality-based error detection
- Patent number 10,528,413
- Issue date Jan 7, 2020
- Intel Corporation
- Jun Pin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interleaving scheme for increasing operating efficiency during high...
- Patent number 10,243,561
- Issue date Mar 26, 2019
- Intel Corporation
- Archanna Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed FPGA boot-up through concurrent multi-frame configuratio...
- Patent number 10,186,305
- Issue date Jan 22, 2019
- Altera Corporation
- Jun Pin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed FPGA boot-up through concurrent multi-frame configuratio...
- Patent number 9,627,019
- Issue date Apr 18, 2017
- Altera Corporation
- Jun Pin Tan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed FPGA boot-up through concurrent multi-frame configuratio...
- Patent number 9,401,190
- Issue date Jul 26, 2016
- Altera Corporation
- Jun Pin Tan
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit with state and data retention
- Patent number 9,383,802
- Issue date Jul 5, 2016
- Altera Corporation
- Jun Pin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configuring data registers to program a programmable device with a...
- Patent number 8,941,408
- Issue date Jan 27, 2015
- Altera Corporation
- Jun Pin Tan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit with improved interconnect routing and associate...
- Patent number 8,629,689
- Issue date Jan 14, 2014
- Altera Corporation
- Jun Pin Tan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory error detection circuitry
- Patent number 8,612,814
- Issue date Dec 17, 2013
- Altera Corporation
- Jun Pin Tan
- G11 - INFORMATION STORAGE
Information Patent Grant
Zeroization verification of integrated circuit
- Patent number 8,437,200
- Issue date May 7, 2013
- Altera Corporation
- Jun Pin Tan
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit with configurable test pins
- Patent number 8,327,199
- Issue date Dec 4, 2012
- Altera Corporation
- Jayabrata Ghosh Dastidar
- G01 - MEASURING TESTING
Information Patent Grant
Data encoding scheme to reduce sense current
- Patent number 8,189,362
- Issue date May 29, 2012
- Altera Corporation
- Jun Pin Tan
- G11 - INFORMATION STORAGE
Information Patent Grant
Data encoding scheme to reduce sense current
- Patent number 7,978,493
- Issue date Jul 12, 2011
- Altera Corporation
- Jun Pin Tan
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic real-time delay characterization and configuration
- Patent number 7,787,314
- Issue date Aug 31, 2010
- Altera Corporation
- Jun Pin Tan
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuitry for facilitating performance of multiply-accumulate opera...
- Patent number 7,565,390
- Issue date Jul 21, 2009
- Altera Corporation
- Tat Mun Lui
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Techniques For Storing States Of Signals In Configurable Storage Ci...
- Publication number 20240137026
- Publication date Apr 25, 2024
- Altera Corporation
- Bee Yee Ng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
NON-DESTRUCTIVE READBACK AND WRITEBACK FOR INTEGRATED CIRCUIT DEVICE
- Publication number 20210149601
- Publication date May 20, 2021
- Bee Yee Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE FOR PARALLEL CONFIGURATION OF PROGRAMMABLE DEVICES
- Publication number 20200358444
- Publication date Nov 12, 2020
- Intel Corporation
- Kevin Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HIGH SPEED FPGA BOOT-UP THROUGH CONCURRENT MULTI-FRAME CONFIGURATIO...
- Publication number 20190156873
- Publication date May 23, 2019
- Altera Corporation
- Jun Pin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Sector-Aligned Memory Accessible to Programmable Logic Fabric of Pr...
- Publication number 20190043536
- Publication date Feb 7, 2019
- Intel Corporation
- Scott J. Weber
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTERLEAVING SCHEME FOR INCREASING OPERATING EFFICIENCY DURING HIGH...
- Publication number 20190044514
- Publication date Feb 7, 2019
- Intel Corporation
- Archanna Srinivasan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Configuration or Data Caching for Programmable Logic Device
- Publication number 20190042127
- Publication date Feb 7, 2019
- Intel Corporation
- Scott J. Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ACCESSING CONFIGURABLE MEMORY DURING HARD...
- Publication number 20180336935
- Publication date Nov 22, 2018
- Intel Corporation
- Jun Pin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CRITICALITY-BASED ERROR DETECTION
- Publication number 20180285190
- Publication date Oct 4, 2018
- Intel Corporation
- Jun Pin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR PROGRAMMABLE INTEGRATED CIRCUIT COPROCESS...
- Publication number 20180143860
- Publication date May 24, 2018
- Intel Corporation
- Aravind Dasu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE INTEGRATED CIRCUIT WITH STACKED MEMORY DIE FOR STORING...
- Publication number 20180143777
- Publication date May 24, 2018
- Intel Corporation
- Aravind Dasu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH SPEED FPGA BOOT-UP THROUGH CONCURRENT MULTI-FRAME CONFIGURATIO...
- Publication number 20170221537
- Publication date Aug 3, 2017
- Altera Corporation
- Jun Pin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH SPEED FPGA BOOT-UP THROUGH CONCURRENT MULTI-FRAME CONFIGURATIO...
- Publication number 20160307612
- Publication date Oct 20, 2016
- Altera Corporation
- Jun Pin Tan
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURING DATA REGISTERS TO PROGRAM A PROGRAMMABLE DEVICE WITH A...
- Publication number 20140240000
- Publication date Aug 28, 2014
- Jun Pin Tan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DATA ENCODING SCHEME TO REDUCE SENSE CURRENT
- Publication number 20110292711
- Publication date Dec 1, 2011
- Jun Pin Tan
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC REAL-TIME DELAY CHARACTERIZATION AND CONFIGURATION
- Publication number 20100061166
- Publication date Mar 11, 2010
- Altera Corporation
- Jun Pin Tan
- H03 - BASIC ELECTRONIC CIRCUITRY

Jun Pin Tan

Person

Patents Grantslast 30 patents

Non-destructive readback and writeback for integrated circuit device

Programmable integrated circuit with stacked memory die for storing...

Configuration or data caching for programmable logic device

Sector-aligned memory accessible to programmable logic fabric of pr...

Interface for parallel configuration of programmable devices

Methods and apparatus for accessing configurable memory during hard...

Interface for parallel configuration of programmable devices

Criticality-based error detection

Interleaving scheme for increasing operating efficiency during high...

High speed FPGA boot-up through concurrent multi-frame configuratio...

High speed FPGA boot-up through concurrent multi-frame configuratio...

High speed FPGA boot-up through concurrent multi-frame configuratio...

Integrated circuit with state and data retention

Configuring data registers to program a programmable device with a...

Integrated circuit with improved interconnect routing and associate...

Memory error detection circuitry

Zeroization verification of integrated circuit

Integrated circuit with configurable test pins

Data encoding scheme to reduce sense current

Data encoding scheme to reduce sense current

Dynamic real-time delay characterization and configuration

Circuitry for facilitating performance of multiply-accumulate opera...

Patents Applicationslast 30 patents

Techniques For Storing States Of Signals In Configurable Storage Ci...

NON-DESTRUCTIVE READBACK AND WRITEBACK FOR INTEGRATED CIRCUIT DEVICE

INTERFACE FOR PARALLEL CONFIGURATION OF PROGRAMMABLE DEVICES

HIGH SPEED FPGA BOOT-UP THROUGH CONCURRENT MULTI-FRAME CONFIGURATIO...

Sector-Aligned Memory Accessible to Programmable Logic Fabric of Pr...

INTERLEAVING SCHEME FOR INCREASING OPERATING EFFICIENCY DURING HIGH...

Configuration or Data Caching for Programmable Logic Device

METHODS AND APPARATUS FOR ACCESSING CONFIGURABLE MEMORY DURING HARD...

CRITICALITY-BASED ERROR DETECTION

METHODS AND APPARATUS FOR PROGRAMMABLE INTEGRATED CIRCUIT COPROCESS...

PROGRAMMABLE INTEGRATED CIRCUIT WITH STACKED MEMORY DIE FOR STORING...

HIGH SPEED FPGA BOOT-UP THROUGH CONCURRENT MULTI-FRAME CONFIGURATIO...

HIGH SPEED FPGA BOOT-UP THROUGH CONCURRENT MULTI-FRAME CONFIGURATIO...

CONFIGURING DATA REGISTERS TO PROGRAM A PROGRAMMABLE DEVICE WITH A...

DATA ENCODING SCHEME TO REDUCE SENSE CURRENT

DYNAMIC REAL-TIME DELAY CHARACTERIZATION AND CONFIGURATION