JUN SUNG KANG

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Cavity spacer for nanowire transistors
- Patent number 11,929,396
- Issue date Mar 12, 2024
- Intel Corporation
- William Hsu
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Dielectric isolation layer between a nanowire transistor and a subs...
- Patent number 11,901,458
- Issue date Feb 13, 2024
- Intel Corporation
- Bruce E. Beattie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-planar integrated circuit structures having mitigated source or...
- Patent number 11,869,891
- Issue date Jan 9, 2024
- Intel Corporation
- Jun Sung Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nanowire transistor structure and method of shaping
- Patent number 11,869,973
- Issue date Jan 9, 2024
- Intel Corporation
- Erica J. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned nanowire
- Patent number 11,715,787
- Issue date Aug 1, 2023
- Intel Corporation
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dielectric isolation layer between a nanowire transistor and a subs...
- Patent number 11,404,578
- Issue date Aug 2, 2022
- Intel Corporation
- Bruce E. Beattie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cavity spacer for nanowire transistors
- Patent number 11,342,411
- Issue date May 24, 2022
- Intel Corporation
- William Hsu
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Gate-all-around integrated circuit structures having self-aligned s...
- Patent number 11,276,691
- Issue date Mar 15, 2022
- Intel Corporation
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned nanowire
- Patent number 11,205,715
- Issue date Dec 21, 2021
- Intel Corporation
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming self aligned spacers for nanowire device structures
- Patent number 10,672,868
- Issue date Jun 2, 2020
- Intel Corporation
- Karthik Jambunathan
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Reduced leakage transistors with germanium-rich channel regions
- Patent number 10,516,021
- Issue date Dec 24, 2019
- Intel Corporation
- Glenn A. Glass
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Cavity Spacer for Nanowire Transistors
- Publication number 20240347595
- Publication date Oct 17, 2024
- Intel Corporation
- William Hsu
- B82 - NANO-TECHNOLOGY
Information Patent Application
DIELECTRIC ISOLATION LAYER BETWEEN A NANOWIRE TRANSISTOR AND A SUBS...
- Publication number 20240145598
- Publication date May 2, 2024
- Intel Corporation
- Bruce E. Beattie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-PLANAR INTEGRATED CIRCUIT STRUCTURES HAVING MITIGATED SOURCE OR...
- Publication number 20240096896
- Publication date Mar 21, 2024
- Intel Corporation
- Jun Sung KANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NANOWIRE TRANSISTOR STRUCTURE AND METHOD OF SHAPING
- Publication number 20240088296
- Publication date Mar 14, 2024
- Intel Corporation
- Erica J. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIELECTRIC ISOLATION LAYER BETWEEN A NANOWIRE TRANSISTOR AND A SUBS...
- Publication number 20220336668
- Publication date Oct 20, 2022
- Intel Corporation
- Bruce E. Beattie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAVITY SPACER FOR NANOWIRE TRANSISTORS
- Publication number 20220246721
- Publication date Aug 4, 2022
- Intel Corporation
- William Hsu
- B82 - NANO-TECHNOLOGY
Information Patent Application
SELF-ALIGNED NANOWIRE
- Publication number 20220052178
- Publication date Feb 17, 2022
- Intel Corporation
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED NANOWIRE
- Publication number 20200152767
- Publication date May 14, 2020
- Intel Corporation
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-PLANAR INTEGRATED CIRCUIT STRUCTURES HAVING MITIGATED SOURCE OR...
- Publication number 20200105757
- Publication date Apr 2, 2020
- Intel Corporation
- Jun Sung KANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING SELF-ALIGNED S...
- Publication number 20200091145
- Publication date Mar 19, 2020
- Intel Corporation
- Biswajeet GUHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAVITY SPACER FOR NANOWIRE TRANSISTORS
- Publication number 20200006478
- Publication date Jan 2, 2020
- Intel Corporation
- William Hsu
- B82 - NANO-TECHNOLOGY
Information Patent Application
NANOWIRE TRANSISTOR STRUCTURE AND METHOD OF SHAPING
- Publication number 20190393350
- Publication date Dec 26, 2019
- Intel Corporation
- Erica J. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIELECTRIC ISOLATION LAYER BETWEEN A NANOWIRE TRANSISTOR AND A SUBS...
- Publication number 20190393351
- Publication date Dec 26, 2019
- Intel Corporation
- Bruce E. Beattie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GEOMETRY TUNING OF FIN BASED TRANSISTOR
- Publication number 20190019891
- Publication date Jan 17, 2019
- Intel Corporation
- Glenn A. GLASS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING SELF ALIGNED SPACERS FOR NANOWIRE DEVICE STRUCTURES
- Publication number 20180358436
- Publication date Dec 13, 2018
- Intel Corporation
- Karthik Jambunathan
- B82 - NANO-TECHNOLOGY
Information Patent Application
REDUCED LEAKAGE TRANSISTORS WITH GERMANIUM-RICH CHANNEL REGIONS
- Publication number 20180331184
- Publication date Nov 15, 2018
- Intel Corporation
- GLENN A. GLASS
- H01 - BASIC ELECTRIC ELEMENTS

JUN SUNG KANG

Person

Patents Grantslast 30 patents

Cavity spacer for nanowire transistors

Dielectric isolation layer between a nanowire transistor and a subs...

Non-planar integrated circuit structures having mitigated source or...

Nanowire transistor structure and method of shaping

Self-aligned nanowire

Dielectric isolation layer between a nanowire transistor and a subs...

Cavity spacer for nanowire transistors

Gate-all-around integrated circuit structures having self-aligned s...

Self-aligned nanowire

Methods of forming self aligned spacers for nanowire device structures

Reduced leakage transistors with germanium-rich channel regions

Patents Applicationslast 30 patents

Cavity Spacer for Nanowire Transistors

DIELECTRIC ISOLATION LAYER BETWEEN A NANOWIRE TRANSISTOR AND A SUBS...

NON-PLANAR INTEGRATED CIRCUIT STRUCTURES HAVING MITIGATED SOURCE OR...

NANOWIRE TRANSISTOR STRUCTURE AND METHOD OF SHAPING

DIELECTRIC ISOLATION LAYER BETWEEN A NANOWIRE TRANSISTOR AND A SUBS...

CAVITY SPACER FOR NANOWIRE TRANSISTORS

SELF-ALIGNED NANOWIRE

SELF-ALIGNED NANOWIRE

NON-PLANAR INTEGRATED CIRCUIT STRUCTURES HAVING MITIGATED SOURCE OR...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING SELF-ALIGNED S...

CAVITY SPACER FOR NANOWIRE TRANSISTORS

NANOWIRE TRANSISTOR STRUCTURE AND METHOD OF SHAPING

DIELECTRIC ISOLATION LAYER BETWEEN A NANOWIRE TRANSISTOR AND A SUBS...

GEOMETRY TUNING OF FIN BASED TRANSISTOR

METHODS OF FORMING SELF ALIGNED SPACERS FOR NANOWIRE DEVICE STRUCTURES

REDUCED LEAKAGE TRANSISTORS WITH GERMANIUM-RICH CHANNEL REGIONS