Jun Zhou

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
System and method for improved placement in custom VLSI circuit des...
- Patent number 8,028,265
- Issue date Sep 27, 2011
- International Business Machines Corporation
- William D. Ramsour
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accurate parasitics estimation for hierarchical customized VLSI design
- Patent number 7,913,216
- Issue date Mar 22, 2011
- International Business Machines Corporation
- Yiu-Hing Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of achieving timing closure in digital integrated circuits b...
- Patent number 7,743,355
- Issue date Jun 22, 2010
- International Business Machines Corporation
- Jun Zhou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid linear wire model approach to tuning transistor widths of ci...
- Patent number 7,325,210
- Issue date Jan 29, 2008
- International Business Machines Corporation
- Vasant Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for tuning a digital design for synthesized random logic cir...
- Patent number 7,093,208
- Issue date Aug 15, 2006
- International Business Machines Corporation
- Patrick M. Williams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of achieving timing closure in digital integrated circuits b...
- Patent number 7,003,747
- Issue date Feb 21, 2006
- International Business Machines Corporation
- Jun Zhou
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
FAST CARRY-CALCULATION ORIENTED REDUNDANCY-TOLERATED FIXED-POINT NU...
- Publication number 20240143327
- Publication date May 2, 2024
- Jun Zhou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of Intelligent Matrix Solving Approach Enhanced with Integra...
- Publication number 20240143692
- Publication date May 2, 2024
- Jun Zhou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Improved Placement in Custom VLSI Circuit Des...
- Publication number 20100031215
- Publication date Feb 4, 2010
- International Business Machines Corporation
- William D. Ramsour
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Accurate Parasitics Estimation for Hierarchical Customized VLSI Design
- Publication number 20090210849
- Publication date Aug 20, 2009
- International Business Machines Corporation
- Yiu-Hing Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of Achieving Timing Closure in Digital Integrated Circuits b...
- Publication number 20080072184
- Publication date Mar 20, 2008
- International Business Machines Corporation
- Jun Zhou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hybrid linear wire model approach to tuning transistor widths of ci...
- Publication number 20060206845
- Publication date Sep 14, 2006
- International Business Machines Corporation
- Vasant Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of achieving timing closure in digital integrated circuits b...
- Publication number 20060150127
- Publication date Jul 6, 2006
- International Business Machines Corporation
- Jun Zhou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for tuning a digital design for synthesized random logic cir...
- Publication number 20040230924
- Publication date Nov 18, 2004
- International Business Machines Corporation
- Patrick M. Williams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of achieving timing closure in digital integrated circuits b...
- Publication number 20040230929
- Publication date Nov 18, 2004
- Jun Zhou
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

System and method for improved placement in custom VLSI circuit des...

Accurate parasitics estimation for hierarchical customized VLSI design

Method of achieving timing closure in digital integrated circuits b...

Hybrid linear wire model approach to tuning transistor widths of ci...

Method for tuning a digital design for synthesized random logic cir...

Method of achieving timing closure in digital integrated circuits b...

Patents Applicationslast 30 patents

FAST CARRY-CALCULATION ORIENTED REDUNDANCY-TOLERATED FIXED-POINT NU...

Method of Intelligent Matrix Solving Approach Enhanced with Integra...

System and Method for Improved Placement in Custom VLSI Circuit Des...

Accurate Parasitics Estimation for Hierarchical Customized VLSI Design

Method of Achieving Timing Closure in Digital Integrated Circuits b...

Hybrid linear wire model approach to tuning transistor widths of ci...

Method of achieving timing closure in digital integrated circuits b...

Method for tuning a digital design for synthesized random logic cir...

Method of achieving timing closure in digital integrated circuits b...