JunWoo Myung

Person

Kyungsangnamdo, KR

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device and method of forming ultra thin multi-die fac...
- Patent number 10,573,600
- Issue date Feb 25, 2020
- STATS ChipPAC Pte. Ltd.
- HeeJo Chi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Semiconductor device and method of forming ultra thin multi-die fac...
- Patent number 9,735,113
- Issue date Aug 15, 2017
- STATS ChipPAC Pte. Ltd.
- HeeJo Chi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package system with molded strip protrusion
- Patent number 8,937,372
- Issue date Jan 20, 2015
- Stats Chippac Ltd.
- Jae Hak Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package system with stacked die
- Patent number 8,810,019
- Issue date Aug 19, 2014
- Stats Chippac Ltd.
- Jae Hak Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with an integral-interposer-str...
- Patent number 8,710,634
- Issue date Apr 29, 2014
- Stats Chippac Ltd.
- HeeJo Chi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacture of inline integrated circuit system
- Patent number 8,501,540
- Issue date Aug 6, 2013
- Stats Chippac Ltd.
- Jae Hak Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with dual side connection and m...
- Patent number 8,421,210
- Issue date Apr 16, 2013
- Stats Chippac Ltd.
- HeeJo Chi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor packaging system with multipart conductive pillars an...
- Patent number 8,304,296
- Issue date Nov 6, 2012
- Stats Chippac Ltd.
- ChanHoon Ko
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing package system incorporating flip-chip ass...
- Patent number 8,183,089
- Issue date May 22, 2012
- Stats Chippac Ltd.
- A Leam Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package system with stacked die
- Patent number 8,138,591
- Issue date Mar 20, 2012
- Stats Chippac Ltd.
- Jae Hak Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Inline integrated circuit system
- Patent number 7,968,981
- Issue date Jun 28, 2011
- Stats Chippac Ltd.
- Jae Hak Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked integrated circuit package system with intra-stack encapsul...
- Patent number 7,871,861
- Issue date Jan 18, 2011
- Stats Chippac Ltd.
- Sungmin Song
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package system incorporating a flip-chip assembly
- Patent number 7,859,120
- Issue date Dec 28, 2010
- Stats Chippac Ltd.
- A Leam Choi
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor Device and Method of Forming Ultra Thin Multi-Die Fac...
- Publication number 20170309572
- Publication date Oct 26, 2017
- STATS ChipPAC Pte Ltd.
- HeeJo Chi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKED DIE
- Publication number 20120133038
- Publication date May 31, 2012
- Jae Hak Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGING SYSTEM WITH MULTIPART CONDUCTIVE PILLARS AN...
- Publication number 20110316155
- Publication date Dec 29, 2011
- ChanHoon Ko
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDE CONNECTION AND M...
- Publication number 20110285009
- Publication date Nov 24, 2011
- HeeJo Chi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Ultra Thin Multi-Die Fac...
- Publication number 20110285007
- Publication date Nov 24, 2011
- STATS ChipPAC, Ltd.
- HeeJo Chi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
METHOD FOR MANUFACTURE OF INLINE INTEGRATED CIRCUIT SYSTEM
- Publication number 20110244635
- Publication date Oct 6, 2011
- Jae Hak Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING PACKAGE SYSTEM INCORPORATING FLIP-CHIP ASS...
- Publication number 20110092021
- Publication date Apr 21, 2011
- A Leam Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTEGRAL-INTERPOSER-STR...
- Publication number 20100244222
- Publication date Sep 30, 2010
- HeeJo Chi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTRA-STACK ENCAPSUL...
- Publication number 20090321908
- Publication date Dec 31, 2009
- Sungmin Song
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SYSTEM
- Publication number 20090283889
- Publication date Nov 19, 2009
- Byoung Wook Jang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE SYSTEM INCORPORATING A FLIP-CHIP ASSEMBLY
- Publication number 20090283888
- Publication date Nov 19, 2009
- A Leam Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INLINE INTEGRATED CIRCUIT SYSTEM
- Publication number 20090258494
- Publication date Oct 15, 2009
- Jae Hak Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOLDED STRIP PROTRUSION
- Publication number 20080230883
- Publication date Sep 25, 2008
- Jae Hak Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKED DIE
- Publication number 20080073770
- Publication date Mar 27, 2008
- Jae Hak Yee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SPACERLESS SEMICONDUCTOR PACKAGE CHIP STACKING SYSTEM
- Publication number 20070268660
- Publication date Nov 22, 2007
- STATS ChipPAC Ltd.
- Seungyun Ahn
- H01 - BASIC ELECTRIC ELEMENTS

JunWoo Myung

Person

Patents Grantslast 30 patents

Semiconductor device and method of forming ultra thin multi-die fac...

Semiconductor device and method of forming ultra thin multi-die fac...

Integrated circuit package system with molded strip protrusion

Integrated circuit package system with stacked die

Integrated circuit packaging system with an integral-interposer-str...

Method for manufacture of inline integrated circuit system

Integrated circuit packaging system with dual side connection and m...

Semiconductor packaging system with multipart conductive pillars an...

Method for manufacturing package system incorporating flip-chip ass...

Integrated circuit package system with stacked die

Inline integrated circuit system

Stacked integrated circuit package system with intra-stack encapsul...

Package system incorporating a flip-chip assembly

Patents Applicationslast 30 patents

Semiconductor Device and Method of Forming Ultra Thin Multi-Die Fac...

INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKED DIE

SEMICONDUCTOR PACKAGING SYSTEM WITH MULTIPART CONDUCTIVE PILLARS AN...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDE CONNECTION AND M...

Semiconductor Device and Method of Forming Ultra Thin Multi-Die Fac...

METHOD FOR MANUFACTURE OF INLINE INTEGRATED CIRCUIT SYSTEM

METHOD FOR MANUFACTURING PACKAGE SYSTEM INCORPORATING FLIP-CHIP ASS...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTEGRAL-INTERPOSER-STR...

STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTRA-STACK ENCAPSUL...

INTEGRATED CIRCUIT PACKAGE SYSTEM

PACKAGE SYSTEM INCORPORATING A FLIP-CHIP ASSEMBLY

INLINE INTEGRATED CIRCUIT SYSTEM

INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOLDED STRIP PROTRUSION

INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKED DIE

SPACERLESS SEMICONDUCTOR PACKAGE CHIP STACKING SYSTEM