Jyh-Chyum Guo

Person

Hsinchu Hsien, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Method for parameter extraction of a semiconductor device
- Patent number 10,345,371
- Issue date Jul 9, 2019
- National Chiao Tung University
- Jyh-Chyurn Guo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parameter extraction method for semiconductor device
- Patent number 8,691,599
- Issue date Apr 8, 2014
- National Chiao Tung University
- Jyh-Chyurn Guo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for passing particles on selected areas on a wafer
- Patent number 7,071,478
- Issue date Jul 4, 2006
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Wen Chin Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interpolation filter structure
- Patent number 7,002,997
- Issue date Feb 21, 2006
- Winbond Electronics Corp.
- Yu-Cheng Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Gate stack for high performance sub-micron CMOS devices
- Patent number 6,894,357
- Issue date May 17, 2005
- Taiwan Semiconductor Manufacturing Company
- Jyh-Chyurn Guo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device and method for providing shielding in radio frequency integr...
- Patent number 6,888,063
- Issue date May 3, 2005
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wai-Yi Lien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ground-signal-ground pad layout for device tester structure
- Patent number 6,878,964
- Issue date Apr 12, 2005
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wai-Yi Lien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration method to enhance p+ gate activation
- Patent number 6,878,583
- Issue date Apr 12, 2005
- Taiwan Semiconductor Manufacturing Company
- Jyh-Chyurn Guo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-floating body device with enhanced performance
- Patent number 6,847,098
- Issue date Jan 25, 2005
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Horng-Huei Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate electrode doping method for forming semiconductor integrated c...
- Patent number 6,835,622
- Issue date Dec 28, 2004
- Taiwan Semiconductor Manufacturing Co., Ltd
- Ling-Yen Yeh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pre-LDD wet clean recipe to gain channel length scaling margin beyo...
- Patent number 6,660,635
- Issue date Dec 9, 2003
- Taiwan Semiconductor Manufacturing Company
- Jyh-Chyurn Guo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a non-floating body device with enhanced perf...
- Patent number 6,627,515
- Issue date Sep 30, 2003
- Taiwan Semiconductor Manufacturing Company
- Horng-Huei Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating field effect transistor (FET) device with as...
- Patent number 6,596,594
- Issue date Jul 22, 2003
- Taiwan Semiconductor Manufacturing Co., Ltd
- Jyh-Chyurn Guo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate stack for high performance sub-micron CMOS devices
- Patent number 6,596,599
- Issue date Jul 22, 2003
- Taiwan Semiconductor Manufacturing Company
- Jyh-Chyurn Guo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test structures for measuring DRAM cell node junction leakage current
- Patent number 6,529,427
- Issue date Mar 4, 2003
- Vanguard International Semiconductor Corporation
- Jyh-Chyurn Guo
- G11 - INFORMATION STORAGE
Information Patent Grant
Sacrificial spacer layer method for fabricating field effect transi...
- Patent number 6,528,376
- Issue date Mar 4, 2003
- Taiwan Semiconductor Manufacturing Co., Ltd
- Jyh-Chyurn Guo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming asymmetric wells for DRAM cells
- Patent number 6,380,045
- Issue date Apr 30, 2002
- Vanguard International Semiconductor Corp.
- Jyh-Chyum Guo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing floating gate memory with substrate band-to...
- Patent number 6,352,886
- Issue date Mar 5, 2002
- Macronix International Co., Ltd.
- Jyh-Chyurn Guo
- G11 - INFORMATION STORAGE
Information Patent Grant
Inverse source/drain process using disposable sidewall spacer
- Patent number 6,323,077
- Issue date Nov 27, 2001
- Vanguard International Semiconductor Corporation
- Jyh-chyurn Guo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming asymmetric source/drain for a DRAM cell
- Patent number 6,297,105
- Issue date Oct 2, 2001
- Vanguard International Semiconductor Corporation
- Jyh-Chyum Guo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form ultra-shallow buried-channel MOSFETs
- Patent number 6,103,580
- Issue date Aug 15, 2000
- Vanguard International Semiconductor Corporation
- Jyh-Chyurn Guo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Floating gate memory with substrate band-to-band tunneling induced...
- Patent number 6,009,017
- Issue date Dec 28, 1999
- Macronix International Co., Ltd.
- Jyh-Chyurn Guo
- G11 - INFORMATION STORAGE
Information Patent Grant
Process for manufacturing a dual floating gate oxide flash memory cell
- Patent number 5,918,125
- Issue date Jun 29, 1999
- Macronix International Co., Ltd.
- Jyh-Chyurn Guo
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR PARAMETER EXTRACTION OF A SEMICONDUCTOR DEVICE
- Publication number 20170242065
- Publication date Aug 24, 2017
- NATIONAL CHIAO-TUNG UNIVERSITY
- Jyh-Chyurn GUO
- G01 - MEASURING TESTING
Information Patent Application
Parameter extraction method for semiconductor device
- Publication number 20120197593
- Publication date Aug 2, 2012
- NATIONAL CHIAO-TUNG UNIVERSITY
- Jyh-Chyurn Guo
- G01 - MEASURING TESTING
Information Patent Application
System and method for passing particles on selected areas on a wafer
- Publication number 20050218346
- Publication date Oct 6, 2005
- Wen Chin Lin
- B82 - NANO-TECHNOLOGY
Information Patent Application
DEVICE AND METHOD FOR PROVIDING SHIELDING IN RADIO FREQUENCY INTEGR...
- Publication number 20050082075
- Publication date Apr 21, 2005
- Taiwan Semiconductor Manufacturing Co., LTD
- Wai-Yi Lien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GROUND-SIGNAL-GROUND PAD LAYOUT FOR DEVICE TESTER STRUCTURE
- Publication number 20050067616
- Publication date Mar 31, 2005
- Wai-Yi Lien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integration method to enhance p+ gate activation
- Publication number 20040152253
- Publication date Aug 5, 2004
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
- Jyh Chyurn Guo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Gate electrode doping method for forming semiconductor integrated c...
- Publication number 20030232473
- Publication date Dec 18, 2003
- Taiwn Semiconductor Manufacturing Co., Ltd.
- Ling-Yen Yeh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Gate stack for high performance sub-micron CMOS devices
- Publication number 20030211684
- Publication date Nov 13, 2003
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
- Jyh-Chyurn Guo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interpolation filter structure
- Publication number 20030002542
- Publication date Jan 2, 2003
- Yu-Cheng Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Floating gate memory with substrate band-to-band tunneling induced...
- Publication number 20010002052
- Publication date May 31, 2001
- Jyh-Chyurn Guo
- H01 - BASIC ELECTRIC ELEMENTS

Jyh-Chyum Guo

Person

Patents Grantslast 30 patents

Method for parameter extraction of a semiconductor device

Parameter extraction method for semiconductor device

System and method for passing particles on selected areas on a wafer

Interpolation filter structure

Gate stack for high performance sub-micron CMOS devices

Device and method for providing shielding in radio frequency integr...

Ground-signal-ground pad layout for device tester structure

Integration method to enhance p+ gate activation

Non-floating body device with enhanced performance

Gate electrode doping method for forming semiconductor integrated c...

Pre-LDD wet clean recipe to gain channel length scaling margin beyo...

Method of fabricating a non-floating body device with enhanced perf...

Method for fabricating field effect transistor (FET) device with as...

Gate stack for high performance sub-micron CMOS devices

Test structures for measuring DRAM cell node junction leakage current

Sacrificial spacer layer method for fabricating field effect transi...

Method of forming asymmetric wells for DRAM cells

Method of manufacturing floating gate memory with substrate band-to...

Inverse source/drain process using disposable sidewall spacer

Method of forming asymmetric source/drain for a DRAM cell

Method to form ultra-shallow buried-channel MOSFETs

Floating gate memory with substrate band-to-band tunneling induced...

Process for manufacturing a dual floating gate oxide flash memory cell

Patents Applicationslast 30 patents

METHOD FOR PARAMETER EXTRACTION OF A SEMICONDUCTOR DEVICE

Parameter extraction method for semiconductor device

System and method for passing particles on selected areas on a wafer

DEVICE AND METHOD FOR PROVIDING SHIELDING IN RADIO FREQUENCY INTEGR...

GROUND-SIGNAL-GROUND PAD LAYOUT FOR DEVICE TESTER STRUCTURE

Integration method to enhance p+ gate activation

Gate electrode doping method for forming semiconductor integrated c...

Gate stack for high performance sub-micron CMOS devices

Interpolation filter structure

Floating gate memory with substrate band-to-band tunneling induced...