Jyotirmoy Saikia

Person

Pachatia, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Scheme for masking output of scan chains in test circuit
- Patent number 10,203,370
- Issue date Feb 12, 2019
- Synopsys, Inc.
- Jyotirmoy Saikia
- G01 - MEASURING TESTING
Information Patent Grant
Handling of undesirable distribution of unknown values in testing o...
- Patent number 10,067,187
- Issue date Sep 4, 2018
- Synopsys, Inc.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Grant
Scheme for masking output of scan chains in test circuit
- Patent number 9,588,179
- Issue date Mar 7, 2017
- Synopsys, Inc.
- Jyotirmoy Saikia
- G01 - MEASURING TESTING
Information Patent Grant
Scheme for masking output of scan chains in test circuit
- Patent number 9,417,287
- Issue date Aug 16, 2016
- Synopsys, Inc.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Grant
Test design optimizer for configurable scan architectures
- Patent number 8,954,918
- Issue date Feb 10, 2015
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Grant
Test design optimizer for configurable scan architectures
- Patent number 8,584,073
- Issue date Nov 12, 2013
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Grant
Accelerating automatic test pattern generation in a multi-core comp...
- Patent number 8,521,464
- Issue date Aug 27, 2013
- Synopsys, Inc.
- Ashwin Kumar
- G01 - MEASURING TESTING
Information Patent Grant
Test architecture including cyclical cache chains, selective bypass...
- Patent number 8,479,067
- Issue date Jul 2, 2013
- Synopsys, Inc.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Grant
Implementing hierarchical design-for-test logic for modular circuit...
- Patent number 8,065,651
- Issue date Nov 22, 2011
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Scheme for Masking Output of Scan Chains in Test Circuit
- Publication number 20170131354
- Publication date May 11, 2017
- Synopsys, Inc.
- Jyotirmoy Saikia
- G01 - MEASURING TESTING
Information Patent Application
Scheme for Masking Output of Scan Chains in Test Circuit
- Publication number 20160341795
- Publication date Nov 24, 2016
- Synopsys, Inc.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Application
Handling of Undesirable Distribution of Unknown Values in Testing o...
- Publication number 20150025819
- Publication date Jan 22, 2015
- Synopsys, Inc.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Application
Scheme for Masking Output of Scan Chains in Test Circuit
- Publication number 20140372822
- Publication date Dec 18, 2014
- Jyotirmoy Saikia
- G01 - MEASURING TESTING
Information Patent Application
Scheme for Masking Output of Scan Chains in Test Circuit
- Publication number 20140317463
- Publication date Oct 23, 2014
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Application
TEST DESIGN OPTIMIZER FOR CONFIGURABLE SCAN ARCHITECTURES
- Publication number 20140059399
- Publication date Feb 27, 2014
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Application
Accelerating Automatic Test Pattern Generation in a Multi-Core Comp...
- Publication number 20110301907
- Publication date Dec 8, 2011
- Synopsys, Inc.
- Ashwin Kumar
- G01 - MEASURING TESTING
Information Patent Application
Test Architecture Including Cyclical Cache Chains, Selective Bypass...
- Publication number 20110258498
- Publication date Oct 20, 2011
- Synopsys, Inc.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING A HIERARCHICAL DESIGN-FOR-TES...
- Publication number 20100192030
- Publication date Jul 29, 2010
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Application
TEST DESIGN OPTIMIZER FOR CONFIGURABLE SCAN ARCHITECTURES
- Publication number 20100017760
- Publication date Jan 21, 2010
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING

Jyotirmoy Saikia

Person

Patents Grantslast 30 patents

Scheme for masking output of scan chains in test circuit

Handling of undesirable distribution of unknown values in testing o...

Scheme for masking output of scan chains in test circuit

Scheme for masking output of scan chains in test circuit

Test design optimizer for configurable scan architectures

Test design optimizer for configurable scan architectures

Accelerating automatic test pattern generation in a multi-core comp...

Test architecture including cyclical cache chains, selective bypass...

Implementing hierarchical design-for-test logic for modular circuit...

Patents Applicationslast 30 patents

Scheme for Masking Output of Scan Chains in Test Circuit

Scheme for Masking Output of Scan Chains in Test Circuit

Handling of Undesirable Distribution of Unknown Values in Testing o...

Scheme for Masking Output of Scan Chains in Test Circuit

Scheme for Masking Output of Scan Chains in Test Circuit

TEST DESIGN OPTIMIZER FOR CONFIGURABLE SCAN ARCHITECTURES

Accelerating Automatic Test Pattern Generation in a Multi-Core Comp...

Test Architecture Including Cyclical Cache Chains, Selective Bypass...

METHOD AND APPARATUS FOR IMPLEMENTING A HIERARCHICAL DESIGN-FOR-TES...

TEST DESIGN OPTIMIZER FOR CONFIGURABLE SCAN ARCHITECTURES