Jyuh-Fuh Lin

Person

Chunan Township, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Method of fabricating an integrated circuit with non-printable dumm...
- Patent number 11,061,317
- Issue date Jul 13, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jyuh-Fuh Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of fabricating an integrated circuit with a pattern density-...
- Patent number 10,811,225
- Issue date Oct 20, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jyuh-Fuh Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating an integrated circuit with a pattern density-...
- Patent number 10,431,423
- Issue date Oct 1, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jyuh-Fuh Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating an integrated circuit with non-printable dumm...
- Patent number 10,359,695
- Issue date Jul 23, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jyuh-Fuh Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of fabricating an integrated circuit with a pattern density-...
- Patent number 10,170,276
- Issue date Jan 1, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jyuh-Fuh Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and technique for rasterizing circuit layout data
- Patent number 9,658,538
- Issue date May 23, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Pei-Yi Liu
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method of fabricating an integrated circuit with non-printable dumm...
- Patent number 9,594,862
- Issue date Mar 14, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jyuh-Fuh Lin
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method of fabricating an integrated circuit with a pattern density-...
- Patent number 9,552,964
- Issue date Jan 24, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jyuh-Fuh Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating an integrated circuit with block dummy for op...
- Patent number 9,436,788
- Issue date Sep 6, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jyuh-Fuh Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of fabricating an integrated circuit with optimized pattern...
- Patent number 9,436,787
- Issue date Sep 6, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jyuh-Fuh Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detecting method for forming semiconductor device
- Patent number 8,755,045
- Issue date Jun 17, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jyuh-Fuh Lin
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH A PATTERN DENSITY-...
- Publication number 20200027699
- Publication date Jan 23, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jyuh-Fuh LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Fabricating an Integrated Circuit with Non-Printable Dumm...
- Publication number 20190339610
- Publication date Nov 7, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jyuh-Fuh Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH A PATTERN DENSITY-...
- Publication number 20190214227
- Publication date Jul 11, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jyuh-Fuh LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH A PATTERN DENSITY-...
- Publication number 20170186584
- Publication date Jun 29, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jyuh-Fuh LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Fabricating an Integrated Circuit With Non-Printable Dumm...
- Publication number 20170176849
- Publication date Jun 22, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jyuh-Fuh Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND TECHNIQUE FOR RASTERIZING CIRCUIT LAYOUT DATA
- Publication number 20160180005
- Publication date Jun 23, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Pei-Yi Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of Fabricating an Integrated Circuit with a Pattern Density-...
- Publication number 20150371821
- Publication date Dec 24, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jyuh-Fuh Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Fabricating an Integrated Circuit with Non-Printable Dumm...
- Publication number 20150370942
- Publication date Dec 24, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jyuh-Fuh Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of Fabricating an Integrated Circuit with Block Dummy for Op...
- Publication number 20150294057
- Publication date Oct 15, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jyuh-Fuh Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of Fabricating an Integrated Circuit with Optimized Pattern...
- Publication number 20150294056
- Publication date Oct 15, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jyuh-Fuh Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETECTING METHOD FOR FORMING SEMICONDUCTOR DEVICE
- Publication number 20130176558
- Publication date Jul 11, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jyuh-Fuh Lin
- G01 - MEASURING TESTING

Jyuh-Fuh Lin

Person

Patents Grantslast 30 patents

Method of fabricating an integrated circuit with non-printable dumm...

Method of fabricating an integrated circuit with a pattern density-...

Method of fabricating an integrated circuit with a pattern density-...

Method of fabricating an integrated circuit with non-printable dumm...

Method of fabricating an integrated circuit with a pattern density-...

System and technique for rasterizing circuit layout data

Method of fabricating an integrated circuit with non-printable dumm...

Method of fabricating an integrated circuit with a pattern density-...

Method of fabricating an integrated circuit with block dummy for op...

Method of fabricating an integrated circuit with optimized pattern...

Detecting method for forming semiconductor device

Patents Applicationslast 30 patents

METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH A PATTERN DENSITY-...

Method of Fabricating an Integrated Circuit with Non-Printable Dumm...

METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH A PATTERN DENSITY-...

METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH A PATTERN DENSITY-...

Method of Fabricating an Integrated Circuit With Non-Printable Dumm...

SYSTEM AND TECHNIQUE FOR RASTERIZING CIRCUIT LAYOUT DATA

Method of Fabricating an Integrated Circuit with a Pattern Density-...

Method of Fabricating an Integrated Circuit with Non-Printable Dumm...

Method of Fabricating an Integrated Circuit with Block Dummy for Op...

Method of Fabricating an Integrated Circuit with Optimized Pattern...

DETECTING METHOD FOR FORMING SEMICONDUCTOR DEVICE