Ka Fai Chang

Person

Hsin-Chu City, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Layout design methodology for stacked devices
- Patent number 12,027,513
- Issue date Jul 2, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- Fong-yuan Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system of forming integrated circuit
- Patent number 12,009,260
- Issue date Jun 11, 2024
- Taiwan Semiconductor Manufacturing Company Ltd.
- Ka Fai Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout design methodology for stacked devices
- Patent number 11,756,951
- Issue date Sep 12, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Fong-yuan Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Electromagnetic shielding metal-insulator-metal capacitor structure
- Patent number 11,694,973
- Issue date Jul 4, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Hui Yu Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of forming entangled inductor structures
- Patent number 11,545,298
- Issue date Jan 3, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Ka Fai Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layout design methodology for stacked devices
- Patent number 11,222,884
- Issue date Jan 11, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd
- Fong-Yuan Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Electromagnetic shielding metal-insulator-metal capacitor structure
- Patent number 11,088,084
- Issue date Aug 10, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd
- Hui Yu Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Solenoid inductors within a multi-chip package
- Patent number 10,971,485
- Issue date Apr 6, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hui Yu Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Entangled inductor structures
- Patent number 10,943,729
- Issue date Mar 9, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ka Fai Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system of forming integrated circuit
- Patent number 10,811,316
- Issue date Oct 20, 2020
- Taiwan Semiconductor Manufacturing Company Ltd.
- Ka Fai Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electromagnetic shielding metal-insulator-metal capacitor structure
- Patent number 10,665,550
- Issue date May 26, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Hui Yu Lee
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
LAYOUT DESIGN METHODOLOGY FOR STACKED DEVICES
- Publication number 20240312978
- Publication date Sep 19, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Fong-Yuan CHANG
- G11 - INFORMATION STORAGE
Information Patent Application
Layout Design Methodology For Stacked Devices
- Publication number 20230361104
- Publication date Nov 9, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Fong-Yuan Chang
- G11 - INFORMATION STORAGE
Information Patent Application
LAYOUT DESIGN METHODOLOGY FOR STACKED DEVICES
- Publication number 20220130818
- Publication date Apr 28, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Fong-Yuan Chang
- G11 - INFORMATION STORAGE
Information Patent Application
ELECTROMAGNETIC SHIELDING METAL-INSULATOR-METAL CAPACITOR STRUCTURE
- Publication number 20210320072
- Publication date Oct 14, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hui Yu LEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENTANGLED INDUCTOR STRUCTURES
- Publication number 20210257156
- Publication date Aug 19, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ka Fai CHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND SYSTEM OF FORMING INTEGRATED CIRCUIT
- Publication number 20200402856
- Publication date Dec 24, 2020
- Taiwan Semiconductor Manufacturing company Ltd.
- KA FAI CHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTROMAGNETIC SHIELDING METAL-INSULATOR-METAL CAPACITOR STRUCTURE
- Publication number 20200258846
- Publication date Aug 13, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hui Yu LEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT DESIGN METHODOLOGY FOR STACKED DEVICES
- Publication number 20200168595
- Publication date May 28, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Fong-Yuan CHANG
- G11 - INFORMATION STORAGE
Information Patent Application
SOLENOID INDUCTORS WITHIN A MULTI-CHIP PACKAGE
- Publication number 20200135709
- Publication date Apr 30, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hui Yu LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENTANGLED INDUCTOR STRUCTURES
- Publication number 20200135388
- Publication date Apr 30, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ka Fai CHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND SYSTEM OF FORMING INTEGRATED CIRCUIT
- Publication number 20200051863
- Publication date Feb 13, 2020
- Taiwan Semiconductor Manufacturing company Ltd.
- KA FAI CHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTROMAGNETIC SHIELDING METAL-INSULATOR-METAL CAPACITOR STRUCTURE
- Publication number 20200020644
- Publication date Jan 16, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hui Yu LEE
- G06 - COMPUTING CALCULATING COUNTING

Ka Fai Chang

Person

Patents Grantslast 30 patents

Layout design methodology for stacked devices

Method and system of forming integrated circuit

Layout design methodology for stacked devices

Electromagnetic shielding metal-insulator-metal capacitor structure

Method of forming entangled inductor structures

Layout design methodology for stacked devices

Electromagnetic shielding metal-insulator-metal capacitor structure

Solenoid inductors within a multi-chip package

Entangled inductor structures

Method and system of forming integrated circuit

Electromagnetic shielding metal-insulator-metal capacitor structure

Patents Applicationslast 30 patents

LAYOUT DESIGN METHODOLOGY FOR STACKED DEVICES

Layout Design Methodology For Stacked Devices

LAYOUT DESIGN METHODOLOGY FOR STACKED DEVICES

ELECTROMAGNETIC SHIELDING METAL-INSULATOR-METAL CAPACITOR STRUCTURE

ENTANGLED INDUCTOR STRUCTURES

METHOD AND SYSTEM OF FORMING INTEGRATED CIRCUIT

ELECTROMAGNETIC SHIELDING METAL-INSULATOR-METAL CAPACITOR STRUCTURE

LAYOUT DESIGN METHODOLOGY FOR STACKED DEVICES

SOLENOID INDUCTORS WITHIN A MULTI-CHIP PACKAGE

ENTANGLED INDUCTOR STRUCTURES

METHOD AND SYSTEM OF FORMING INTEGRATED CIRCUIT

ELECTROMAGNETIC SHIELDING METAL-INSULATOR-METAL CAPACITOR STRUCTURE