Kai Chirca

Person

Dallas, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Virtual network pre-arbitration for deadlock avoidance and enhanced...
- Patent number 12,182,398
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Matthew David Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Nested loop control
- Patent number 12,175,244
- Issue date Dec 24, 2024
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore shared cache operation engine
- Patent number 12,159,030
- Issue date Dec 3, 2024
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable cache for coherent system
- Patent number 12,141,435
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherence shared state suppression
- Patent number 12,135,646
- Issue date Nov 5, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming engine with deferred exception reporting
- Patent number 12,099,400
- Issue date Sep 24, 2024
- Texas Instruments Incorporated
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore bus architecture with non-blocking high performance trans...
- Patent number 12,072,824
- Issue date Aug 27, 2024
- Texas Instruments Incorporated
- David M. Thompson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Highly integrated scalable, flexible DSP megamodule architecture
- Patent number 12,072,812
- Issue date Aug 27, 2024
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache management operations using streaming engine
- Patent number 12,050,914
- Issue date Jul 30, 2024
- Texas Instruments Incorporated
- Joseph Raymond Michael Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Nested loop control
- Patent number 11,972,236
- Issue date Apr 30, 2024
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing fundamental computational primitives using a matrix mu...
- Patent number 11,960,567
- Issue date Apr 16, 2024
- Texas Instruments Incorporated
- Arthur John Redfern
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory pipeline control in a hierarchical memory system
- Patent number 11,940,918
- Issue date Mar 26, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-processor bridge with cache allocate awareness
- Patent number 11,907,528
- Issue date Feb 20, 2024
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing device with a microbranch target buffer for branch predi...
- Patent number 11,875,155
- Issue date Jan 16, 2024
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software-hardware memory management modes
- Patent number 11,853,225
- Issue date Dec 26, 2023
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for addressing data in memory
- Patent number 11,836,494
- Issue date Dec 5, 2023
- Texas Instruments Incorporated
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delayed snoop for improved multi-process false sharing parallel thr...
- Patent number 11,822,786
- Issue date Nov 21, 2023
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Nested loop control
- Patent number 11,816,485
- Issue date Nov 14, 2023
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore bus architecture with wire reduction and physical congest...
- Patent number 11,803,505
- Issue date Oct 31, 2023
- Texas Instruments Incorporated
- David M. Thompson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Slot/sub-slot prefetch architecture for multiple memory requestors
- Patent number 11,789,872
- Issue date Oct 17, 2023
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implied fence on stream open
- Patent number 11,782,718
- Issue date Oct 10, 2023
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore shared cache operation engine
- Patent number 11,755,203
- Issue date Sep 12, 2023
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable cache for multi-endpoint heterogeneous coherent system
- Patent number 11,720,248
- Issue date Aug 8, 2023
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for interrupting and resuming execution on an unprotected...
- Patent number 11,693,661
- Issue date Jul 4, 2023
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual network pre-arbitration for deadlock avoidance and enhanced...
- Patent number 11,687,238
- Issue date Jun 27, 2023
- Texas Instmments Incorporated
- Matthew David Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherence shared state suppression
- Patent number 11,675,700
- Issue date Jun 13, 2023
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory pipeline control in a hierarchical memory system
- Patent number 11,580,024
- Issue date Feb 14, 2023
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
User mode event handling
- Patent number 11,573,802
- Issue date Feb 7, 2023
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming engine with deferred exception reporting
- Patent number 11,573,847
- Issue date Feb 7, 2023
- Texas Instruments Incorporated
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure master and secure guest endpoint security firewall
- Patent number 11,501,024
- Issue date Nov 15, 2022
- Texas Instruments Incorporated
- Timothy D Anderson
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PROCESSOR ARCHITECTURE WITH MEMORY ACCESS CIRCUIT
- Publication number 20240411703
- Publication date Dec 12, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE MANAGEMENT OPERATIONS USING STREAMING ENGINE
- Publication number 20240385840
- Publication date Nov 21, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Raymond Michael Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NESTED LOOP CONTROL
- Publication number 20240281231
- Publication date Aug 22, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Computational Primitives Using A Matrix Multiplication Accelerator
- Publication number 20240265062
- Publication date Aug 8, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Arthur John Redfern
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM
- Publication number 20240193087
- Publication date Jun 13, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PROCESSOR BRIDGE WITH CACHE ALLOCATE AWARENESS
- Publication number 20240184446
- Publication date Jun 6, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Branch Prediction Using loop Iteration Count
- Publication number 20240152360
- Publication date May 9, 2024
- Texas Instruments Inc.
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOFTWARE-HARDWARE MEMORY MANAGEMENT MODES
- Publication number 20240126703
- Publication date Apr 18, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Timothy D. ANDERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR ADDRESSING DATA IN MEMORY
- Publication number 20240103863
- Publication date Mar 28, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Timothy David ANDERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DELAYED SNOOP FOR IMPROVED MULTI-PROCESS FALSE SHARING PARALLEL THR...
- Publication number 20240086065
- Publication date Mar 14, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NESTED LOOP CONTROL
- Publication number 20240086193
- Publication date Mar 14, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLIED FENCE ON STREAM OPEN
- Publication number 20240036867
- Publication date Feb 1, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SLOT/SUB-SLOT PREFETCH ARCHITECTURE FOR MULTIPLE MEMORY REQUESTORS
- Publication number 20230418759
- Publication date Dec 28, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICORE SHARED CACHE OPERATION ENGINE
- Publication number 20230418469
- Publication date Dec 28, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE CACHE FOR COHERENT SYSTEM
- Publication number 20230384931
- Publication date Nov 30, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM FOR INTERRUPTING AND RESUMING EXECUTION ON AN UNPROTECTED...
- Publication number 20230350681
- Publication date Nov 2, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Timothy D. ANDERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUAL NETWORK PRE-ARBITRATION FOR DEADLOCK AVOIDANCE AND ENHANCED...
- Publication number 20230325078
- Publication date Oct 12, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Matthew David PIERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE COHERENCE SHARED STATE SUPPRESSION
- Publication number 20230297506
- Publication date Sep 21, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USER MODE EVENT HANDLING
- Publication number 20230185576
- Publication date Jun 15, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STREAMING ENGINE WITH DEFERRED EXCEPTION REPORTING
- Publication number 20230185649
- Publication date Jun 15, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM
- Publication number 20230185719
- Publication date Jun 15, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SECURE MASTER AND SECURE GUEST ENDPOINT SECURITY FIREWALL
- Publication number 20230048071
- Publication date Feb 16, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE EVENT TESTING
- Publication number 20230022869
- Publication date Jan 26, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CREDIT AWARE CENTRAL ARBITRATION FOR MULTI-ENDPOINT, MULTI-CORE SYSTEM
- Publication number 20220374356
- Publication date Nov 24, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Matthew David PIERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER
- Publication number 20220374357
- Publication date Nov 24, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Matthew David PIERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EVENT HANDLING IN PIPELINE EXECUTE STAGES
- Publication number 20220365787
- Publication date Nov 17, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXIT HISTORY BASED BRANCH PREDICTION
- Publication number 20220326954
- Publication date Oct 13, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED ERROR DETECTION AND CORRECTION WITH HAMMING CODE HANDOFF
- Publication number 20220283942
- Publication date Sep 8, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PROCESSOR, MULTI-DOMAIN, MULTI-PROTOCOL, CACHE COHERENT, SPEC...
- Publication number 20220269607
- Publication date Aug 25, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICORE BUS ARCHITECTURE WITH WIRE REDUCTION AND PHYSICAL CONGEST...
- Publication number 20220261373
- Publication date Aug 18, 2022
- TEXAS INSTRUMENTS INCORPORATED
- David M. Thompson
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Virtual network pre-arbitration for deadlock avoidance and enhanced...

Nested loop control

Multicore shared cache operation engine

Configurable cache for coherent system

Cache coherence shared state suppression

Streaming engine with deferred exception reporting

Multicore bus architecture with non-blocking high performance trans...

Highly integrated scalable, flexible DSP megamodule architecture

Cache management operations using streaming engine

Nested loop control

Implementing fundamental computational primitives using a matrix mu...

Memory pipeline control in a hierarchical memory system

Multi-processor bridge with cache allocate awareness

Processing device with a microbranch target buffer for branch predi...

Software-hardware memory management modes

System and method for addressing data in memory

Delayed snoop for improved multi-process false sharing parallel thr...

Nested loop control

Multicore bus architecture with wire reduction and physical congest...

Slot/sub-slot prefetch architecture for multiple memory requestors

Implied fence on stream open

Multicore shared cache operation engine

Configurable cache for multi-endpoint heterogeneous coherent system

Mechanism for interrupting and resuming execution on an unprotected...

Virtual network pre-arbitration for deadlock avoidance and enhanced...

Cache coherence shared state suppression

Memory pipeline control in a hierarchical memory system

User mode event handling

Streaming engine with deferred exception reporting

Secure master and secure guest endpoint security firewall

Patents Applicationslast 30 patents

PROCESSOR ARCHITECTURE WITH MEMORY ACCESS CIRCUIT

CACHE MANAGEMENT OPERATIONS USING STREAMING ENGINE

NESTED LOOP CONTROL

Computational Primitives Using A Matrix Multiplication Accelerator

MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM

MULTI-PROCESSOR BRIDGE WITH CACHE ALLOCATE AWARENESS

Branch Prediction Using loop Iteration Count

SOFTWARE-HARDWARE MEMORY MANAGEMENT MODES

SYSTEM AND METHOD FOR ADDRESSING DATA IN MEMORY

DELAYED SNOOP FOR IMPROVED MULTI-PROCESS FALSE SHARING PARALLEL THR...

NESTED LOOP CONTROL

IMPLIED FENCE ON STREAM OPEN

SLOT/SUB-SLOT PREFETCH ARCHITECTURE FOR MULTIPLE MEMORY REQUESTORS

MULTICORE SHARED CACHE OPERATION ENGINE

CONFIGURABLE CACHE FOR COHERENT SYSTEM

MECHANISM FOR INTERRUPTING AND RESUMING EXECUTION ON AN UNPROTECTED...

VIRTUAL NETWORK PRE-ARBITRATION FOR DEADLOCK AVOIDANCE AND ENHANCED...

CACHE COHERENCE SHARED STATE SUPPRESSION

USER MODE EVENT HANDLING

STREAMING ENGINE WITH DEFERRED EXCEPTION REPORTING

MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM

SECURE MASTER AND SECURE GUEST ENDPOINT SECURITY FIREWALL

PROGRAMMABLE EVENT TESTING

CREDIT AWARE CENTRAL ARBITRATION FOR MULTI-ENDPOINT, MULTI-CORE SYSTEM

MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER

EVENT HANDLING IN PIPELINE EXECUTE STAGES

EXIT HISTORY BASED BRANCH PREDICTION

DISTRIBUTED ERROR DETECTION AND CORRECTION WITH HAMMING CODE HANDOFF

MULTI-PROCESSOR, MULTI-DOMAIN, MULTI-PROTOCOL, CACHE COHERENT, SPEC...

MULTICORE BUS ARCHITECTURE WITH WIRE REDUCTION AND PHYSICAL CONGEST...