Kai Liu

Person

Mountain View, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Embedded die redistribution layers for active device
- Patent number 9,443,815
- Issue date Sep 13, 2016
- Maxim Integrated Products, Inc.
- Kai Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Top exposed semiconductor chip package
- Patent number 9,412,684
- Issue date Aug 9, 2016
- Alpha and Omega Semiconductor Incorporated
- Yan Xun Xue
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and configuration for manufacturing flip chip contact (FCC)...
- Patent number 9,337,132
- Issue date May 10, 2016
- Alpha and Omega Semiconductor Incorporated
- Ming Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for top-side cooled semiconductor package with stacked inter...
- Patent number 9,218,987
- Issue date Dec 22, 2015
- ALPHA AND OMEGA SEMICONDUCTER INCORPORATED
- Kai Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked dual chip package having leveling projections
- Patent number 9,165,866
- Issue date Oct 20, 2015
- Alpha and Omega Semiconductor Incorporated
- Hamza Yilmaz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with connecting plate for internal connection
- Patent number 9,147,586
- Issue date Sep 29, 2015
- Alpha & Omega Semiconductor, Inc.
- Jun Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor packaging method using connecting plate for internal...
- Patent number 9,040,357
- Issue date May 26, 2015
- Alpha & Omega Semiconductor, Inc.
- Jun Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package leadframe for dual side assembly
- Patent number 8,951,847
- Issue date Feb 10, 2015
- Intersil Americas LLC
- Nikhil Vishwanath Kelkar
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Dual-leadframe multi-chip package
- Patent number 8,933,549
- Issue date Jan 13, 2015
- Alpha & Omega Semiconductor, Inc.
- Kai Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-layer lead frame package and method of fabrication
- Patent number 8,815,649
- Issue date Aug 26, 2014
- Alpha & Omega Semiconductor Corporation
- Jun Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor packaging and fabrication method using connecting pla...
- Patent number 8,722,466
- Issue date May 13, 2014
- Alpha & Omega Semiconductor, Inc.
- Jun Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-leadframe multi-chip package and method of manufacture
- Patent number 8,709,867
- Issue date Apr 29, 2014
- Alpha and Omega Semiconductor Inc.
- Kai Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductive clip for semiconductor device package
- Patent number 8,680,658
- Issue date Mar 25, 2014
- Alpha and Omega Semiconductor Incorporated
- Lei Shi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked dual chip package and method of fabrication
- Patent number 8,581,376
- Issue date Nov 12, 2013
- Alpha and Omega Semiconductor Incorporated
- Hamza Yilmaz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip chip contact (FCC) power package
- Patent number 8,564,049
- Issue date Oct 22, 2013
- Alpha and Omega Semiconductor Incorporated
- Ming Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power semiconductor device package and fabrication method
- Patent number 8,563,360
- Issue date Oct 22, 2013
- Alpha & Omega Semiconductor, Inc.
- Jun Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-layer lead frame package and method of fabrication
- Patent number 8,513,784
- Issue date Aug 20, 2013
- Alpha and Omega Semiconductor Incorporated
- Jun Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making solder-top enhanced semiconductor device of low p...
- Patent number 8,497,160
- Issue date Jul 30, 2013
- Alpha & Omega Semiconductor, Inc.
- François Hébert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Top exposed clip with window array
- Patent number 8,373,257
- Issue date Feb 12, 2013
- Alpha and Omega Semiconductor Incorporated
- Lei Shi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Top-side cooled semiconductor package with stacked interconnection...
- Patent number 8,354,740
- Issue date Jan 15, 2013
- Alpha & Omega Semiconductor, Inc.
- Kai Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Solder-top enhanced semiconductor device for low parasitic impedanc...
- Patent number 8,264,084
- Issue date Sep 11, 2012
- Alpha & Omega Semiconductor, Inc.
- François Hébert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Compact semiconductor package with integrated bypass capacitor
- Patent number 8,183,662
- Issue date May 22, 2012
- Alpha & Omega Semiconductor, Inc.
- François Hébert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-leadframe multi-chip package and method of manufacture
- Patent number 8,154,108
- Issue date Apr 10, 2012
- Alpha and Omega Semiconductor Incorporated
- Kai Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Compact semiconductor package with integrated bypass capacitor and...
- Patent number 8,062,932
- Issue date Nov 22, 2011
- Alpha & Omega Semiconductor, Inc.
- François Hébert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package having a bridge plate connection
- Patent number 8,053,874
- Issue date Nov 8, 2011
- Alpha and Omega Semiconductor Incorporated
- Ming Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual flat non-leaded semiconductor package
- Patent number 7,951,651
- Issue date May 31, 2011
- Alpha and Omega Semiconductor Incorporated
- Kai Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Compact co-packaged semiconductor dies with elevation-adaptive inte...
- Patent number 7,906,375
- Issue date Mar 15, 2011
- Alpha and Omega Semiconductor Inc.
- Kai Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making semiconductor package with plated connection
- Patent number 7,897,438
- Issue date Mar 1, 2011
- Alpha and Omega Semiconductor Incorporated
- Leeshawn Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package having a bridged plate interconnection
- Patent number 7,884,469
- Issue date Feb 8, 2011
- Alpha and Omega Semiconductor Incorporated
- Lei Shi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a semiconductor device employing electroless...
- Patent number 7,811,904
- Issue date Oct 12, 2010
- Alpha and Omega Semiconductor Incorporated
- Tao Feng
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR PACKAGE WITH ADHESIVE MATERIAL PRE-PRINTED ON THE LEA...
- Publication number 20160126214
- Publication date May 5, 2016
- Xiaotian Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EMBEDDED DIE REDISTRIBUTION LAYERS FOR ACTIVE DEVICE
- Publication number 20150243590
- Publication date Aug 27, 2015
- Maxim Integrated Products, Inc.
- Kai Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLIP CHIP CONTACT (FCC) POWER PACKAGE
- Publication number 20150102425
- Publication date Apr 16, 2015
- Ming Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER SEMICONDUCTOR DEVICE PACKAGE AND FABRICATION METHOD
- Publication number 20150076676
- Publication date Mar 19, 2015
- Jun Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Top-side Cooled Semiconductor Package with Stacked Inter...
- Publication number 20140154843
- Publication date Jun 5, 2014
- Alpha and Omega Semiconductor Incorprated
- Kai Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual-leadframe Multi-chip Package
- Publication number 20140103512
- Publication date Apr 17, 2014
- ALPHA & OMEGA SEMICONDUCTOR INCORPORATED
- Kai Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Packaging Method Using Connecting Plate for Internal...
- Publication number 20140080263
- Publication date Mar 20, 2014
- ALPHA & OMEGA SEMICONDUCTOR INCORPORATED
- Jun Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Package with Connecting Plate for Internal Connection
- Publication number 20140070386
- Publication date Mar 13, 2014
- ALPHA & OMEGA SEMICONDUCTOR INCORPORATED
- Jun Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED DUAL CHIP PACKAGE HAVING LEVELING PROJECTIONS
- Publication number 20140054758
- Publication date Feb 27, 2014
- ALPHA & OMEGA SEMICONDUCTOR INCORPORATED
- Hamza Yilmaz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Top Exposed Semiconductor Chip Package
- Publication number 20140035116
- Publication date Feb 6, 2014
- ALPHA & OMEGA SEMICONDUCTOR INCORPORATED
- Yan Xun Xue
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-LAYER LEAD FRAME PACKAGE AND METHOD OF FABRICATION
- Publication number 20130302946
- Publication date Nov 14, 2013
- Jun Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE LEADFRAME FOR DUAL SIDE ASSEMBLY
- Publication number 20130181332
- Publication date Jul 18, 2013
- INTERSIL AMERICAS LLC
- Nikhil Vishwanath Kelkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Top-side Cooled Semiconductor Package with Stacked Interconnection...
- Publication number 20130099364
- Publication date Apr 25, 2013
- Alpha and Omega Semiconductor Incorprated
- Kai Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Making Solder-top Enhanced Semiconductor Device of Low P...
- Publication number 20120289001
- Publication date Nov 15, 2012
- Francois Hebert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual-leadframe Multi-chip Package and Method of Manufacture
- Publication number 20120161304
- Publication date Jun 28, 2012
- Kai Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Compact Semiconductor Package with Integrated Bypass Capacitor
- Publication number 20120032244
- Publication date Feb 9, 2012
- Francois Hebert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual-leadframe Multi-chip Package and Method of Manufacture
- Publication number 20110233746
- Publication date Sep 29, 2011
- Kai Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-LAYER LEAD FRAME PACKAGE AND METHOD OF FABRICATION
- Publication number 20110227205
- Publication date Sep 22, 2011
- Jun Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED DUAL CHIP PACKAGE AND METHOD OF FABRICATION
- Publication number 20110227207
- Publication date Sep 22, 2011
- ALPHA & OMEGA SEMICONDUCTOR INCORPORATED
- Hamza Yilmaz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Packaging and Fabrication Method Using Connecting Pla...
- Publication number 20110221008
- Publication date Sep 15, 2011
- Jun Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor package with adhesive material pre-printed on the lea...
- Publication number 20110068457
- Publication date Mar 24, 2011
- Xiaotian Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER SEMICONDUCTOR DEVICE PACKAGE AND FABRICATION METHOD
- Publication number 20100308454
- Publication date Dec 9, 2010
- Jun Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Compact Co-packaged Semiconductor Dies with Elevation-adaptive Inte...
- Publication number 20100273294
- Publication date Oct 28, 2010
- Kai Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Compact Semiconductor Package with Integrated Bypass Capacitor and...
- Publication number 20100133674
- Publication date Jun 3, 2010
- Francois Hebert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Top-side Cooled Semiconductor Package with Stacked Interconnection...
- Publication number 20100133670
- Publication date Jun 3, 2010
- Kai Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Compact Co-packaged Semiconductor Dies with Elevation-adaptive Inte...
- Publication number 20100032819
- Publication date Feb 11, 2010
- Kai Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE CLIP FOR SEMICONDUCTOR DEVICE PACKAGE
- Publication number 20090294934
- Publication date Dec 3, 2009
- ALPHA & OMEGA SEMICONDUCTOR, LTD.
- Lei Shi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DFN semiconductor package having reduced electrical resistance
- Publication number 20090258458
- Publication date Oct 15, 2009
- Xiaotian Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE HAVING A BRIDGED PLATE INTERCONNECTION
- Publication number 20090236708
- Publication date Sep 24, 2009
- Lei Shi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL FLAT NON-LEADED SEMICONDUCTOR PACKAGE
- Publication number 20090233403
- Publication date Sep 17, 2009
- Kai Liu
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Embedded die redistribution layers for active device

Top exposed semiconductor chip package

Methods and configuration for manufacturing flip chip contact (FCC)...

Method for top-side cooled semiconductor package with stacked inter...

Stacked dual chip package having leveling projections

Semiconductor package with connecting plate for internal connection

Semiconductor packaging method using connecting plate for internal...

Package leadframe for dual side assembly

Dual-leadframe multi-chip package

Multi-layer lead frame package and method of fabrication

Semiconductor packaging and fabrication method using connecting pla...

Dual-leadframe multi-chip package and method of manufacture

Conductive clip for semiconductor device package

Stacked dual chip package and method of fabrication

Flip chip contact (FCC) power package

Power semiconductor device package and fabrication method

Multi-layer lead frame package and method of fabrication

Method for making solder-top enhanced semiconductor device of low p...

Top exposed clip with window array

Top-side cooled semiconductor package with stacked interconnection...

Solder-top enhanced semiconductor device for low parasitic impedanc...

Compact semiconductor package with integrated bypass capacitor

Dual-leadframe multi-chip package and method of manufacture

Compact semiconductor package with integrated bypass capacitor and...

Semiconductor package having a bridge plate connection

Dual flat non-leaded semiconductor package

Compact co-packaged semiconductor dies with elevation-adaptive inte...

Method of making semiconductor package with plated connection

Semiconductor package having a bridged plate interconnection

Method of fabricating a semiconductor device employing electroless...

Patents Applicationslast 30 patents

SEMICONDUCTOR PACKAGE WITH ADHESIVE MATERIAL PRE-PRINTED ON THE LEA...

EMBEDDED DIE REDISTRIBUTION LAYERS FOR ACTIVE DEVICE

FLIP CHIP CONTACT (FCC) POWER PACKAGE

POWER SEMICONDUCTOR DEVICE PACKAGE AND FABRICATION METHOD

Method for Top-side Cooled Semiconductor Package with Stacked Inter...

Dual-leadframe Multi-chip Package

Semiconductor Packaging Method Using Connecting Plate for Internal...

Semiconductor Package with Connecting Plate for Internal Connection

STACKED DUAL CHIP PACKAGE HAVING LEVELING PROJECTIONS

Top Exposed Semiconductor Chip Package

MULTI-LAYER LEAD FRAME PACKAGE AND METHOD OF FABRICATION

PACKAGE LEADFRAME FOR DUAL SIDE ASSEMBLY

Top-side Cooled Semiconductor Package with Stacked Interconnection...

Method for Making Solder-top Enhanced Semiconductor Device of Low P...

Dual-leadframe Multi-chip Package and Method of Manufacture

Compact Semiconductor Package with Integrated Bypass Capacitor

Dual-leadframe Multi-chip Package and Method of Manufacture

MULTI-LAYER LEAD FRAME PACKAGE AND METHOD OF FABRICATION

STACKED DUAL CHIP PACKAGE AND METHOD OF FABRICATION

Semiconductor Packaging and Fabrication Method Using Connecting Pla...

Semiconductor package with adhesive material pre-printed on the lea...

POWER SEMICONDUCTOR DEVICE PACKAGE AND FABRICATION METHOD

Compact Co-packaged Semiconductor Dies with Elevation-adaptive Inte...

Compact Semiconductor Package with Integrated Bypass Capacitor and...

Top-side Cooled Semiconductor Package with Stacked Interconnection...

Compact Co-packaged Semiconductor Dies with Elevation-adaptive Inte...

CONDUCTIVE CLIP FOR SEMICONDUCTOR DEVICE PACKAGE

DFN semiconductor package having reduced electrical resistance

SEMICONDUCTOR PACKAGE HAVING A BRIDGED PLATE INTERCONNECTION

DUAL FLAT NON-LEADED SEMICONDUCTOR PACKAGE