Kailash PAWAR

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Endpoint path margin based integrated circuit design using sub-crit...
- Patent number 11,797,739
- Issue date Oct 24, 2023
- Synopsys, Inc.
- Deyuan Guo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latency offset in pre-clock tree synthesis modeling
- Patent number 11,681,842
- Issue date Jun 20, 2023
- Synopsys, Inc.
- Kailash Pawar
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
LATENCY OFFSET IN PRE-CLOCK TREE SYNTHESIS MODELING
- Publication number 20220180031
- Publication date Jun 9, 2022
- Synopsys, Inc.
- Kailash PAWAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENDPOINT PATH MARGIN BASED INTEGRATED CIRCUIT DESIGN USING SUB-CRIT...
- Publication number 20220092245
- Publication date Mar 24, 2022
- Synopsys, Inc.
- Deyuan GUO
- G06 - COMPUTING CALCULATING COUNTING