Kaiyu Chen

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Divergent control flow for fused EUs
- Patent number 10,699,362
- Issue date Jun 30, 2020
- Intel Corporation
- Pratik J. Ashar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software scoreboard information and synchronization
- Patent number 10,692,170
- Issue date Jun 23, 2020
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor register data re-use mechanism
- Patent number 10,636,112
- Issue date Apr 28, 2020
- Intel Corporation
- Slawomir Grajewski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor register renaming mechanism
- Patent number 10,565,670
- Issue date Feb 18, 2020
- Intel Corporation
- Kaiyu Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global optimal path determination utilizing parallel processing
- Patent number 10,515,431
- Issue date Dec 24, 2019
- Intel Corporation
- Yuenian Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software scoreboard information and synchronization
- Patent number 10,360,654
- Issue date Jul 23, 2019
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient preemption for graphics processors
- Patent number 10,282,227
- Issue date May 7, 2019
- Intel Corporation
- Guei-Yuan Lueh
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CROSS-THREAD REGISTER SHARING FOR MATRIX MULTIPLICATION COMPUTE
- Publication number 20240168807
- Publication date May 23, 2024
- Intel Corporation
- Jorge Eduardo Parra Osorio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTOLIC ARRAY OF ARBITRARY PHYSICAL AND LOGICAL DEPTH
- Publication number 20220414053
- Publication date Dec 29, 2022
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOFTWARE SCOREBOARD INFORMATION AND SYNCHRONIZATION
- Publication number 20190362460
- Publication date Nov 28, 2019
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR REGISTER DATA RE-USE MECHANISM
- Publication number 20190304056
- Publication date Oct 3, 2019
- Intel Corporation
- Slawomir Grajewski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLOBAL OPTIMAL PATH DETERMINATION UTILIZING PARALLEL PROCESSING
- Publication number 20190180406
- Publication date Jun 13, 2019
- Intel Corporation
- Yuenian Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Graphics Processor Register Renaming Mechanism
- Publication number 20180096446
- Publication date Apr 5, 2018
- Kaiyu Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Divergent Control Flow for Fused EUs
- Publication number 20170372446
- Publication date Dec 28, 2017
- Intel Corporation
- Pratik J. Ashar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT PREEMPTION FOR GRAPHICS PROCESSORS
- Publication number 20160140686
- Publication date May 19, 2016
- Intel Corporation
- GUEI-YUAN LUEH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR PARALLELIZING L...
- Publication number 20130159680
- Publication date Jun 20, 2013
- Wei-yu Chen
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Divergent control flow for fused EUs

Software scoreboard information and synchronization

Graphics processor register data re-use mechanism

Graphics processor register renaming mechanism

Global optimal path determination utilizing parallel processing

Software scoreboard information and synchronization

Efficient preemption for graphics processors

Patents Applicationslast 30 patents

CROSS-THREAD REGISTER SHARING FOR MATRIX MULTIPLICATION COMPUTE

SYSTOLIC ARRAY OF ARBITRARY PHYSICAL AND LOGICAL DEPTH

SOFTWARE SCOREBOARD INFORMATION AND SYNCHRONIZATION

GRAPHICS PROCESSOR REGISTER DATA RE-USE MECHANISM

GLOBAL OPTIMAL PATH DETERMINATION UTILIZING PARALLEL PROCESSING

Graphics Processor Register Renaming Mechanism

Divergent Control Flow for Fused EUs

EFFICIENT PREEMPTION FOR GRAPHICS PROCESSORS

SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR PARALLELIZING L...