Kamesh V. Gadepally

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Shallow self isolated doped implanted silicon process
- Patent number 7,087,503
- Issue date Aug 8, 2006
- National Semiconductor Corporation
- Kamesh Gadepally
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow self isolated doped implanted silicon process
- Patent number 6,908,833
- Issue date Jun 21, 2005
- National Semiconductor Corporation
- Kamesh Gadepally
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing an integrated circuit structure with limit...
- Patent number 6,737,343
- Issue date May 18, 2004
- National Semiconductor Corporation
- Kamesh V. Gadepally
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for manufacturing an integrated circuit structure with meta...
- Patent number 6,329,287
- Issue date Dec 11, 2001
- National Semiconductor Corporation
- Kamesh V. Gadepally
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low stress active area silicon island structure with a non-rectangu...
- Patent number 6,225,666
- Issue date May 1, 2001
- National Semiconductor Corporation
- Kamesh V. Gadepally
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of semiconductor structure having two levels of buried...
- Patent number 5,899,714
- Issue date May 4, 1999
- National Semiconductor Corporation
- Douglas R. Farrenkopf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure having two levels of buried regions
- Patent number 5,889,315
- Issue date Mar 30, 1999
- National Semiconductor Corporation
- Douglas R. Farrenkopf
- H01 - BASIC ELECTRIC ELEMENTS

Kamesh V. Gadepally

Person

Patents Grantslast 30 patents

Shallow self isolated doped implanted silicon process

Shallow self isolated doped implanted silicon process

Method for manufacturing an integrated circuit structure with limit...

Process for manufacturing an integrated circuit structure with meta...

Low stress active area silicon island structure with a non-rectangu...

Fabrication of semiconductor structure having two levels of buried...

Semiconductor structure having two levels of buried regions