Kar Keng Chua

Person

Penang, MY

People

Patents Grantslast 30 patents

Information Patent Grant
Clock signal networks for structured ASIC devices
- Patent number 9,225,335
- Issue date Dec 29, 2015
- Altera Corporation
- Chooi Pei Lim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Application-specific integrated circuit equivalents of programmable...
- Patent number 8,863,061
- Issue date Oct 14, 2014
- Altera Corporation
- Kar Keng Chua
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for providing signal routing control
- Patent number 8,786,308
- Issue date Jul 22, 2014
- Altera Corporation
- Siang Poh Loh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Predicting routability of integrated circuits
- Patent number 8,694,944
- Issue date Apr 8, 2014
- Altera Corporation
- Sze Huey Soo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock signal networks for structured ASIC devices
- Patent number 8,595,658
- Issue date Nov 26, 2013
- Altera Corporation
- Chooi Pei Lim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiplier with built-in accumulator
- Patent number 8,533,250
- Issue date Sep 10, 2013
- Altera Corporation
- Kok Yoong Foo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Application-specific integrated circuit equivalents of programmable...
- Patent number 8,504,963
- Issue date Aug 6, 2013
- Altera Corporation
- Kar Keng Chua
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method to modify an integrated circuit (IC) design
- Patent number 8,352,899
- Issue date Jan 8, 2013
- Altera Corporation
- Kian Chin Yap
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with configurable test pins
- Patent number 8,327,199
- Issue date Dec 4, 2012
- Altera Corporation
- Jayabrata Ghosh Dastidar
- G01 - MEASURING TESTING
Information Patent Grant
Application-specific integrated circuit equivalents of programmable...
- Patent number 8,291,355
- Issue date Oct 16, 2012
- Altera Corporation
- Kar Keng Chua
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Real time feedback compensation of programmable logic memory
- Patent number 8,261,141
- Issue date Sep 4, 2012
- Altera Corporation
- Kok Heng Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data encoding scheme to reduce sense current
- Patent number 8,189,362
- Issue date May 29, 2012
- Altera Corporation
- Jun Pin Tan
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of designing integrated circuits including providing an opti...
- Patent number 8,151,224
- Issue date Apr 3, 2012
- Altera Corporation
- Boon Jin Ang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for performing built-in self-test of receiver channel ha...
- Patent number 8,037,377
- Issue date Oct 11, 2011
- Altera Corporation
- Ie Chen Chia
- G01 - MEASURING TESTING
Information Patent Grant
Data encoding scheme to reduce sense current
- Patent number 7,978,493
- Issue date Jul 12, 2011
- Altera Corporation
- Jun Pin Tan
- G11 - INFORMATION STORAGE
Information Patent Grant
Real time feedback compensation of programmable logic memory
- Patent number 7,882,408
- Issue date Feb 1, 2011
- Altera Corporation
- Kok Heng Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Application-specific integrated circuit equivalents of programmable...
- Patent number 7,870,513
- Issue date Jan 11, 2011
- Altera Corporation
- Kar Keng Chua
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatus for programmably powering down structured app...
- Patent number 7,733,121
- Issue date Jun 8, 2010
- Altera Corporation
- Hee Kong Phoon
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay circuit with delay cells in different orientations
- Patent number 7,683,689
- Issue date Mar 23, 2010
- Altera Corporation
- Tat Mun Lui
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Distributed memory circuitry on structured application-specific int...
- Patent number 7,586,327
- Issue date Sep 8, 2009
- Altera Corporation
- Kok Heng Choe
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock signal networks for structured ASIC devices
- Patent number 7,404,169
- Issue date Jul 22, 2008
- Altera Corporation
- Chooi Pei Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for storing and naming static library cells for lookup by l...
- Patent number 7,363,596
- Issue date Apr 22, 2008
- Altera Corporation
- Ji Park
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for programmably powering down structured app...
- Patent number 7,304,497
- Issue date Dec 4, 2007
- Altera Corporation
- Hee Kong Phoon
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods for creating and expanding libraries of structured ASIC log...
- Patent number 7,246,339
- Issue date Jul 17, 2007
- Altera Corporation
- Jinyong Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Application-specific integrated circuit equivalents of programmable...
- Patent number 7,243,329
- Issue date Jul 10, 2007
- Altera Corporation
- Kar Keng Chua
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods for producing structured application-specific integrated ci...
- Patent number 7,243,315
- Issue date Jul 10, 2007
- Altera Corporation
- Kim Pin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Real time feedback compensation of programmable logic memory
- Patent number 7,164,289
- Issue date Jan 16, 2007
- Altera Corporation
- Kok Heng Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable Logic with Pipelined Memory Operation
- Patent number 7,071,731
- Issue date Jul 4, 2006
- Altera Corporation
- Kok Heng Choe
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage-based timing control of memory bit lines
- Patent number 7,046,566
- Issue date May 16, 2006
- Altera Corporation
- Kok Heng Choe
- G11 - INFORMATION STORAGE
Information Patent Grant
Isolation testing scheme for multi-die packages
- Patent number 6,599,764
- Issue date Jul 29, 2003
- Altera Corporation
- Boon Jin Ang
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES
- Publication number 20140077839
- Publication date Mar 20, 2014
- Altera Corporation
- Chooi Pei Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE...
- Publication number 20130314122
- Publication date Nov 28, 2013
- Altera Corporation
- Kar Keng Chua
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE...
- Publication number 20130002295
- Publication date Jan 3, 2013
- Altera Corporation
- Kar Keng Chua
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DATA ENCODING SCHEME TO REDUCE SENSE CURRENT
- Publication number 20110292711
- Publication date Dec 1, 2011
- Jun Pin Tan
- G11 - INFORMATION STORAGE
Information Patent Application
APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE...
- Publication number 20110084727
- Publication date Apr 14, 2011
- Kar Keng Chua
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES
- Publication number 20080258772
- Publication date Oct 23, 2008
- Altera Corporation
- Chooi Pei Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for programmably powering down structured appl...
- Publication number 20080106300
- Publication date May 8, 2008
- Altera Corporation
- Hee Kong Phoon
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Application-specific integrated circuit equivalents of programmable...
- Publication number 20070210827
- Publication date Sep 13, 2007
- Kar Keng Chua
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Methods and apparatus for programmably powering down structured app...
- Publication number 20060279330
- Publication date Dec 14, 2006
- Hee Kong Phoon
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock signal networks for structured ASIC devices
- Publication number 20060267661
- Publication date Nov 30, 2006
- Chooi Pei Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods for producing structured application-specific integrated ci...
- Publication number 20060271899
- Publication date Nov 30, 2006
- Altera Corporation
- Kim Pin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods for creating and expanding libraries of structured ASIC log...
- Publication number 20060230376
- Publication date Oct 12, 2006
- Altera Corporation
- Jinyong Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Application-specific integrated circuit equivalents of programmable...
- Publication number 20060001444
- Publication date Jan 5, 2006
- Kar Keng Chua
- H03 - BASIC ELECTRONIC CIRCUITRY

Kar Keng Chua

Person

Patents Grantslast 30 patents

Clock signal networks for structured ASIC devices

Application-specific integrated circuit equivalents of programmable...

Method and apparatus for providing signal routing control

Predicting routability of integrated circuits

Clock signal networks for structured ASIC devices

Multiplier with built-in accumulator

Application-specific integrated circuit equivalents of programmable...

Method to modify an integrated circuit (IC) design

Integrated circuit with configurable test pins

Application-specific integrated circuit equivalents of programmable...

Real time feedback compensation of programmable logic memory

Data encoding scheme to reduce sense current

Method of designing integrated circuits including providing an opti...

Techniques for performing built-in self-test of receiver channel ha...

Data encoding scheme to reduce sense current

Real time feedback compensation of programmable logic memory

Application-specific integrated circuit equivalents of programmable...

Methods and apparatus for programmably powering down structured app...

Delay circuit with delay cells in different orientations

Distributed memory circuitry on structured application-specific int...

Clock signal networks for structured ASIC devices

Methods for storing and naming static library cells for lookup by l...

Methods and apparatus for programmably powering down structured app...

Methods for creating and expanding libraries of structured ASIC log...

Application-specific integrated circuit equivalents of programmable...

Methods for producing structured application-specific integrated ci...

Real time feedback compensation of programmable logic memory

Programmable Logic with Pipelined Memory Operation

Voltage-based timing control of memory bit lines

Isolation testing scheme for multi-die packages

Patents Applicationslast 30 patents

CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES

APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE...

APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE...

DATA ENCODING SCHEME TO REDUCE SENSE CURRENT

APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE...

CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES

Method and apparatus for programmably powering down structured appl...

Application-specific integrated circuit equivalents of programmable...

Methods and apparatus for programmably powering down structured app...

Clock signal networks for structured ASIC devices

Methods for producing structured application-specific integrated ci...

Methods for creating and expanding libraries of structured ASIC log...

Application-specific integrated circuit equivalents of programmable...