Karan Kacker

Person

Atlanta, GA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Construction of reliable stacked via in electronic substrates—verti...
- Patent number 9,099,458
- Issue date Aug 4, 2015
- International Business Machines Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Construction of reliable stacked via in electronic substrates—verti...
- Patent number 8,866,026
- Issue date Oct 21, 2014
- International Business Machines Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Variable interconnect geometry for electronic packages and fabricat...
- Patent number 8,766,449
- Issue date Jul 1, 2014
- Georgia Tech Research Corporation
- Suresh K. Sitaraman
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Clustered stacked vias for reliable electronic substrates
- Patent number 8,522,430
- Issue date Sep 3, 2013
- International Business Macines Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Compliant off-chip interconnects for use in electronic packages and...
- Patent number 8,382,489
- Issue date Feb 26, 2013
- Georgia Tech Research Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Construction of reliable stacked via in electronic substrates—verti...
- Patent number 8,258,410
- Issue date Sep 4, 2012
- International Business Machines Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Clustered stacked vias for reliable electronic substrates
- Patent number 8,242,593
- Issue date Aug 14, 2012
- International Business Machines Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Compliant off-chip interconnects for use in electronic packages
- Patent number 8,206,160
- Issue date Jun 26, 2012
- Georgia Tech Research Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
CONSTRUCTION OF RELIABLE STACKED VIA IN ELECTRONIC SUBSTRATES - VER...
- Publication number 20120299195
- Publication date Nov 29, 2012
- International Business Machines Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
CLUSTERED STACKED VIAS FOR RELIABLE ELECTRONIC SUBSTRATES
- Publication number 20120279061
- Publication date Nov 8, 2012
- International Business Machines Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
CONSTRUCTION OF RELIABLE STACKED VIA IN ELECTRONIC SUBSTRATES - VER...
- Publication number 20120267158
- Publication date Oct 25, 2012
- International Business Machines Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Compliant Off-Chip Interconnects for Use in Electronic Packages and...
- Publication number 20120192418
- Publication date Aug 2, 2012
- Georgia Tech Research Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
EMBEDDED CONSTRAINER DISCS FOR RELIABLE STACKED VIAS IN ELECTRONIC...
- Publication number 20090189289
- Publication date Jul 30, 2009
- International Business Machines Corporation
- Karan Kacker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Construction of Reliable Stacked Via in Electronic Substrates - Ver...
- Publication number 20090188705
- Publication date Jul 30, 2009
- International Business Machines Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
CLUSTERED STACKED VIAS FOR RELIABLE ELECTRONIC SUBSTRATES
- Publication number 20090189290
- Publication date Jul 30, 2009
- International Business Machines Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Complant off-chip interconnects for use in electronic packages and...
- Publication number 20080305653
- Publication date Dec 11, 2008
- Georgia Tech Research Corporation
- Karan Kacker
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Variable interconnect geometry for electronic packages and fabricat...
- Publication number 20080245559
- Publication date Oct 9, 2008
- Georgia Tech Research Corporation
- Suresh K. Sitaraman
- H01 - BASIC ELECTRIC ELEMENTS

Karan Kacker

Person

Patents Grantslast 30 patents

Construction of reliable stacked via in electronic substrates—verti...

Construction of reliable stacked via in electronic substrates—verti...

Variable interconnect geometry for electronic packages and fabricat...

Clustered stacked vias for reliable electronic substrates

Compliant off-chip interconnects for use in electronic packages and...

Construction of reliable stacked via in electronic substrates—verti...

Clustered stacked vias for reliable electronic substrates

Compliant off-chip interconnects for use in electronic packages

Patents Applicationslast 30 patents

CONSTRUCTION OF RELIABLE STACKED VIA IN ELECTRONIC SUBSTRATES - VER...

CLUSTERED STACKED VIAS FOR RELIABLE ELECTRONIC SUBSTRATES

CONSTRUCTION OF RELIABLE STACKED VIA IN ELECTRONIC SUBSTRATES - VER...

Compliant Off-Chip Interconnects for Use in Electronic Packages and...

EMBEDDED CONSTRAINER DISCS FOR RELIABLE STACKED VIAS IN ELECTRONIC...

Construction of Reliable Stacked Via in Electronic Substrates - Ver...

CLUSTERED STACKED VIAS FOR RELIABLE ELECTRONIC SUBSTRATES

Complant off-chip interconnects for use in electronic packages and...

Variable interconnect geometry for electronic packages and fabricat...