Karthik Subramanian

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Unified approach for improved testing of low power designs with clo...
- Patent number 11,592,481
- Issue date Feb 28, 2023
- Ambarella International LP
- Praveen Kumar Jaini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronized clocks to detect inter-clock domain transition defects
- Patent number 10,739,403
- Issue date Aug 11, 2020
- Ambarella International LP
- Praveen Kumar Jaini
- G01 - MEASURING TESTING
Information Patent Grant
Collapsed forwarding for service domain routers
- Patent number 10,069,725
- Issue date Sep 4, 2018
- Cisco Technology, Inc.
- Dheerendra Talur
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Packet switching label assignment across multiple packet switching...
- Patent number 9,094,335
- Issue date Jul 28, 2015
- Cisco Technology, Inc.
- Karthik Subramanian
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
OPTIMIZED PROTOCOL INDEPENDENT MULTICAST ASSERT MECHANISM
- Publication number 20180367451
- Publication date Dec 20, 2018
- Cisco Technology, Inc.
- Sameer R. Gulrajani
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Packet Switching Label Assignment Across Multiple Packet Switching...
- Publication number 20120213225
- Publication date Aug 23, 2012
- Cisco Technology, Inc. A corporation of California
- Karthik Subramanian
- H04 - ELECTRIC COMMUNICATION TECHNIQUE