Karthik Thambidurai

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Wafer level package device formed using a wafer level lead frame on...
- Patent number 10,304,758
- Issue date May 28, 2019
- MAXIM INTEGRATED PRODUCTS, INC
- Karthik Thambidurai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional chip-to-wafer integration
- Patent number 10,032,749
- Issue date Jul 24, 2018
- Maxim Integrated Products, Inc.
- Amit S. Kelkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level device and method with cantilever pillar structure
- Patent number 9,806,047
- Issue date Oct 31, 2017
- Maxim Integrated Products, Inc.
- Karthik Thambidurai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer-level chip-scale package device having bump assemblies config...
- Patent number 9,721,912
- Issue date Aug 1, 2017
- Maxim Integrated Products, Inc.
- Viren Khandekar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Technique for wafer-level processing of QFN packages
- Patent number 9,472,451
- Issue date Oct 18, 2016
- Maxim Integrated Products, Inc.
- Viren Khandekar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low-cost low-profile solder bump process for enabling ultra-thin wa...
- Patent number 9,425,064
- Issue date Aug 23, 2016
- Karthik Thambidurai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer-level passive device integration
- Patent number 9,324,687
- Issue date Apr 26, 2016
- Maxim Integrated Products, Inc.
- Amit S. Kelkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional chip-to-wafer integration
- Patent number 9,190,391
- Issue date Nov 17, 2015
- Maxim Integrated Products, Inc.
- Amit Subhash Kelkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for wafer-level processing of QFN packages
- Patent number 9,040,408
- Issue date May 26, 2015
- Maxim Integrated Products, Inc.
- Tiao Zhou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for wafer-level processing of QFN packages
- Patent number 8,860,222
- Issue date Oct 14, 2014
- Maxim Integrated Products, Inc.
- Viren Khandekar
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
THREE-DIMENSIONAL CHIP-TO-WAFER INTEGRATION
- Publication number 20160071826
- Publication date Mar 10, 2016
- Maxim Integrated Products, Inc.
- Amit S. Kelkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL DEVICE AND METHOD WITH CANTILEVER PILLAR STRUCTURE
- Publication number 20150279799
- Publication date Oct 1, 2015
- Maxim Integrated Products, Inc.
- Karthik Thambidurai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUE FOR WAFER-LEVEL PROCESSING OF QFN PACKAGES
- Publication number 20150028475
- Publication date Jan 29, 2015
- Maxim Integrated Products, Inc.
- Viren Khandekar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER-LEVEL CHIP-SCALE PACKAGE DEVICE HAVING BUMP ASSEMBLIES CONFIG...
- Publication number 20150008576
- Publication date Jan 8, 2015
- Maxim Integrated Products, Inc.
- Viren Khandekar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW-COST LOW-PROFILE SOLDER BUMP PROCESS FOR ENABLING ULTRA-THIN WA...
- Publication number 20140167252
- Publication date Jun 19, 2014
- Maxim Integrated Products, Inc.
- Karthik Thambidurai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR WAFER-LEVEL PROCESSING OF QFN PACKAGES
- Publication number 20130161817
- Publication date Jun 27, 2013
- Maxim Integrated Products, Inc.
- Viren Khandekar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL CHIP-TO-WAFER INTEGRATION
- Publication number 20130105966
- Publication date May 2, 2013
- MAXIM INTEGRATED PRODUCTS, INC.
- Amit Subhash Kelkar
- H01 - BASIC ELECTRIC ELEMENTS

Karthik Thambidurai

Person

Patents Grantslast 30 patents

Wafer level package device formed using a wafer level lead frame on...

Three-dimensional chip-to-wafer integration

Wafer level device and method with cantilever pillar structure

Wafer-level chip-scale package device having bump assemblies config...

Technique for wafer-level processing of QFN packages

Low-cost low-profile solder bump process for enabling ultra-thin wa...

Wafer-level passive device integration

Three-dimensional chip-to-wafer integration

Techniques for wafer-level processing of QFN packages

Techniques for wafer-level processing of QFN packages

Patents Applicationslast 30 patents

THREE-DIMENSIONAL CHIP-TO-WAFER INTEGRATION

WAFER LEVEL DEVICE AND METHOD WITH CANTILEVER PILLAR STRUCTURE

TECHNIQUE FOR WAFER-LEVEL PROCESSING OF QFN PACKAGES

WAFER-LEVEL CHIP-SCALE PACKAGE DEVICE HAVING BUMP ASSEMBLIES CONFIG...

LOW-COST LOW-PROFILE SOLDER BUMP PROCESS FOR ENABLING ULTRA-THIN WA...

TECHNIQUES FOR WAFER-LEVEL PROCESSING OF QFN PACKAGES

THREE-DIMENSIONAL CHIP-TO-WAFER INTEGRATION