Karthik Thucanakkenpalayam Sundararajan

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Buffer circuitry for store to load forwarding
- Patent number 12,147,707
- Issue date Nov 19, 2024
- Synopsys, Inc.
- Karthik Thucanakkenpalayam Sundararajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Management circuitry for a least recently used memory management pr...
- Patent number 12,124,379
- Issue date Oct 22, 2024
- Synopsys, Inc.
- Karthik Thucanakkenpalayam Sundararajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Predicting aliasing bits in a virtually indexed physically tagged c...
- Patent number 12,124,375
- Issue date Oct 22, 2024
- Synopsys, Inc.
- Karthik Thucanakkenpalayam Sundararajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Conversion of a clean unique request to a read unique request by a...
- Patent number 12,045,167
- Issue date Jul 23, 2024
- Synopsys, Inc.
- Karthik Thucanakkenpalayam Sundararajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Varied validity bit placement in tag bits of a memory
- Patent number 12,026,094
- Issue date Jul 2, 2024
- Synopsys, Inc.
- Karthik Thucanakkenpalayam Sundararajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic correction of single bit errors within a memory
- Patent number 11,928,024
- Issue date Mar 12, 2024
- Synopsys, Inc.
- Karthik Thucanakkenpalayam Sundararajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Energy efficient tag partitioning in cache memory
- Patent number 11,899,586
- Issue date Feb 13, 2024
- Synopsys, Inc.
- Karthik Thucanakkenpalayam Sundararajan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY COHERENCE PROTOCOL FOR COMMUNICATING DATA ASSOCIATED WITH A...
- Publication number 20240143506
- Publication date May 2, 2024
- Synopsys, Inc.
- Karthik THUCANAKKENPALAYAM SUNDARARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VARIED VALIDITY BIT PLACEMENT IN TAG BITS OF A MEMORY
- Publication number 20240143503
- Publication date May 2, 2024
- Synopsys, Inc.
- Karthik THUCANAKKENPALAYAM SUNDARARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONVERSION OF A CLEAN UNIQUE REQUEST TO A READ UNIQUE REQUEST BY A...
- Publication number 20240119004
- Publication date Apr 11, 2024
- Synopsys, Inc.
- Karthik THUCANAKKENPALAYAM SUNDARARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGEMENT CIRCUITRY FOR A LEAST RECENTLY USED MEMORY MANAGEMENT PR...
- Publication number 20240119007
- Publication date Apr 11, 2024
- Synopsys, Inc.
- Karthik THUCANAKKENPALAYAM SUNDARARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFLICT DETECTION AND ADDRESS ARBITRATION FOR ROUTING SCATTER AND...
- Publication number 20240118811
- Publication date Apr 11, 2024
- Synopsys, Inc.
- Karthik THUCANAKKENPALAYAM SUNDARARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORE INSTRUCTION MERGING WITH PATTERN DETECTION
- Publication number 20240111537
- Publication date Apr 4, 2024
- Synopsys, Inc.
- Karthik THUCANAKKENPALAYAM SUNDARARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUFFER CIRCUITRY FOR STORE TO LOAD FORWARDING
- Publication number 20240103761
- Publication date Mar 28, 2024
- Synopsys, Inc.
- Karthik THUCANAKKENPALAYAM SUNDARARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC CORRECTION OF SINGLE BIT ERRORS WITHIN A MEMORY
- Publication number 20240070019
- Publication date Feb 29, 2024
- Synopsys, Inc.
- Karthik THUCANAKKENPALAYAM SUNDARARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient Memory Organization
- Publication number 20150100733
- Publication date Apr 9, 2015
- Synopsys, Inc.
- Carlos Basto
- G06 - COMPUTING CALCULATING COUNTING

Karthik Thucanakkenpalayam Sundararajan

Person

Patents Grantslast 30 patents

Buffer circuitry for store to load forwarding

Management circuitry for a least recently used memory management pr...

Predicting aliasing bits in a virtually indexed physically tagged c...

Conversion of a clean unique request to a read unique request by a...

Varied validity bit placement in tag bits of a memory

Atomic correction of single bit errors within a memory

Energy efficient tag partitioning in cache memory

Patents Applicationslast 30 patents

MEMORY COHERENCE PROTOCOL FOR COMMUNICATING DATA ASSOCIATED WITH A...

VARIED VALIDITY BIT PLACEMENT IN TAG BITS OF A MEMORY

CONVERSION OF A CLEAN UNIQUE REQUEST TO A READ UNIQUE REQUEST BY A...

MANAGEMENT CIRCUITRY FOR A LEAST RECENTLY USED MEMORY MANAGEMENT PR...

CONFLICT DETECTION AND ADDRESS ARBITRATION FOR ROUTING SCATTER AND...

STORE INSTRUCTION MERGING WITH PATTERN DETECTION

BUFFER CIRCUITRY FOR STORE TO LOAD FORWARDING

ATOMIC CORRECTION OF SINGLE BIT ERRORS WITHIN A MEMORY

Efficient Memory Organization