Katsuji Tabara

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Akiruno, JP

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Patents Grantslast 30 patents

Information Patent Grant
Multilayer interconnection structure and method for forming the same
- Patent number 7,514,355
- Issue date Apr 7, 2009
- Fujitsu Microelectronics Limited
- Syuji Katase
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having a dummy pattern
- Patent number 7,242,095
- Issue date Jul 10, 2007
- Fujitsu Limited
- Katsuji Tabara
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Multilayer interconnection structure and method for forming the same
- Publication number 20050287800
- Publication date Dec 29, 2005
- FUJITSU LIMITED
- Syuji Katase
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device having a dummy pattern
- Publication number 20050173802
- Publication date Aug 11, 2005
- FUJITSU LIMITED
- Katsuji Tabara
- H01 - BASIC ELECTRIC ELEMENTS