Kazutaka Miyano

Person

Tokyo, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatuses and methods for deactivating a delay locked loop update...
- Patent number 11,676,650
- Issue date Jun 13, 2023
- Micron Technology, Inc.
- Kazutaka Miyano
- G11 - INFORMATION STORAGE
Information Patent Grant
Selectively controlling clock transmission to a data (DQ) system
- Patent number 11,348,633
- Issue date May 31, 2022
- Micron Technology, Inc.
- Kazutaka Miyano
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for adjusting delay of command signal path
- Patent number 11,087,806
- Issue date Aug 10, 2021
- Micron Technology, Inc.
- Kazutaka Miyano
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for deactivating a delay locked loop update...
- Patent number 11,049,543
- Issue date Jun 29, 2021
- Micron Technology, Inc.
- Kazutaka Miyano
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatuses and methods for data transmission offset values in burs...
- Patent number 10,931,270
- Issue date Feb 23, 2021
- Micron Technology, Inc.
- Yasuo Satoh
- G11 - INFORMATION STORAGE
Information Patent Grant
Shifter circuits having registers arranged in a folded topology
- Patent number 10,924,097
- Issue date Feb 16, 2021
- Micron Technology, Inc.
- Kazutaka Miyano
- G11 - INFORMATION STORAGE
Information Patent Grant
Selectively controlling clock transmission to a data (DQ) system
- Patent number 10,892,002
- Issue date Jan 12, 2021
- Micron Technology, Inc.
- Kazutaka Miyano
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatuses including command delay adjustment circuit
- Patent number 10,755,758
- Issue date Aug 25, 2020
- Micron Technology, Inc.
- Shuichi Ishibashi
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for command synchronization in a memory device
- Patent number 10,636,463
- Issue date Apr 28, 2020
- Micron Technology, Inc.
- Yoshiya Komatsu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Shifter circuits having registers arranged in a folded topology
- Patent number 10,608,620
- Issue date Mar 31, 2020
- Micron Technology, Inc.
- Kazutaka Miyano
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatuses and methods for data transmission offset values in burs...
- Patent number 10,516,391
- Issue date Dec 24, 2019
- Micron Technology, Inc.
- Yasuo Satoh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for command synchronization in a memory device
- Patent number 10,403,340
- Issue date Sep 3, 2019
- Micron Technology, Inc.
- Yoshiya Komatsu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatuses including command delay adjustment circuit
- Patent number 10,290,336
- Issue date May 14, 2019
- Micron Technology, Inc.
- Shuichi Ishibashi
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for adjusting delay of command signal path
- Patent number 9,997,220
- Issue date Jun 12, 2018
- Micron Technology, Inc.
- Kazutaka Miyano
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatuses including command delay adjustment circuit
- Patent number 9,865,317
- Issue date Jan 9, 2018
- Micron Technology, Inc.
- Shuichi Ishibashi
- G11 - INFORMATION STORAGE
Information Patent Grant
Output signal generation device having a phase adjustment unit and...
- Patent number 9,570,149
- Issue date Feb 14, 2017
- Longitude Semiconductor S.a.r.l.
- Kazutaka Miyano
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatuses including command latency control circuit
- Patent number 9,531,363
- Issue date Dec 27, 2016
- Micron Technology, Inc.
- Kazutaka Miyano
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock generating circuit, semiconductor device including the same,...
- Patent number 9,438,251
- Issue date Sep 6, 2016
- PS4 Luxco S.A.R.L.
- Kazutaka Miyano
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device
- Patent number 9,196,349
- Issue date Nov 24, 2015
- Micron Technology, Inc.
- Kazutaka Miyano
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device
- Patent number 9,053,779
- Issue date Jun 9, 2015
- Micron Technology, Inc.
- Kazutaka Miyano
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock generating circuit, semiconductor device including the same,...
- Patent number 9,007,861
- Issue date Apr 14, 2015
- PS4 Luxco S.A.R.L.
- Kazutaka Miyano
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device and information processing system including an...
- Patent number 8,917,563
- Issue date Dec 23, 2014
- PS4 Luxco S.A.R.L.
- Kazutaka Miyano
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device having DLL circuit
- Patent number 8,732,512
- Issue date May 20, 2014
- Kazutaka Miyano
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device and method of controlling the same
- Patent number 8,564,361
- Issue date Oct 22, 2013
- Elpida Memory, Inc.
- Hitoshi Tanaka
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Internal-clock adjusting circuit
- Patent number 8,487,671
- Issue date Jul 16, 2013
- Elpida Memory, Inc.
- Kazutaka Miyano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DLL circuit, semiconductor device including the same, and data proc...
- Patent number 8,482,326
- Issue date Jul 9, 2013
- Elpida Memory, Inc.
- Kazutaka Miyano
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor device and method of controlling the same
- Patent number 8,446,214
- Issue date May 21, 2013
- Elpida Memory, Inc.
- Hitoshi Tanaka
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Clock generating circuit, semiconductor device including the same,...
- Patent number 8,344,773
- Issue date Jan 1, 2013
- Elpida Memory, Inc.
- Kazutaka Miyano
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor device having level shift circuit, control method the...
- Patent number 8,164,372
- Issue date Apr 24, 2012
- Elpida Memory, Inc.
- Shingo Mitsubori
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock control circuit and semiconductor device including the same
- Patent number 8,164,370
- Issue date Apr 24, 2012
- Elpida Memory, Inc.
- Kazutaka Miyano
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Apparatuses And Methods For Deactivating A Delay Locked Loop Update...
- Publication number 20210358541
- Publication date Nov 18, 2021
- Micron Technology, Inc.
- Kazutaka Miyano
- G11 - INFORMATION STORAGE
Information Patent Application
SELECTIVELY CONTROLLING CLOCK TRANSMISSION TO A DATA (DQ) SYSTEM
- Publication number 20210125658
- Publication date Apr 29, 2021
- Micron Technology, Inc.
- Kazutaka Miyano
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR DEACTIVATING A DELAY LOCKED LOOP UPDATE...
- Publication number 20210065782
- Publication date Mar 4, 2021
- Micron Technology, Inc.
- Kazutaka Miyano
- G11 - INFORMATION STORAGE
Information Patent Application
SHIFTER CIRCUITS HAVING REGISTERS ARRANGED IN A FOLDED TOPOLOGY
- Publication number 20200228107
- Publication date Jul 16, 2020
- Micron Technology, Inc.
- Kazutaka Miyano
- G11 - INFORMATION STORAGE
Information Patent Application
SELECTIVELY CONTROLLING CLOCK TRANSMISSION TO A DATA (DQ) SYSTEM
- Publication number 20200135257
- Publication date Apr 30, 2020
- Micron Technology, Inc.
- Kazutaka Miyano
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUSES AND METHODS FOR DATA TRANSMISSION OFFSET VALUES IN BURS...
- Publication number 20200136600
- Publication date Apr 30, 2020
- Micron Technology, Inc.
- Yasuo Satoh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SHIFTER CIRCUITS HAVING REGISTERS ARRANGED IN A FOLDED TOPOLOGY
- Publication number 20190386648
- Publication date Dec 19, 2019
- Micron Technology, Inc.
- Kazutaka Miyano
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TECHNIQUES FOR COMMAND SYNCHRONIZATION IN A MEMORY DEVICE
- Publication number 20190272862
- Publication date Sep 5, 2019
- Micron Technology, Inc.
- Yoshiya Komatsu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TECHNIQUES FOR COMMAND SYNCHRONIZATION IN A MEMORY DEVICE
- Publication number 20190244644
- Publication date Aug 8, 2019
- Micron Technology, Inc.
- Yoshiya Komatsu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUSES AND METHODS FOR DATA TRANSMISSION OFFSET VALUES IN BURS...
- Publication number 20190181847
- Publication date Jun 13, 2019
- Micron Technology, Inc.
- Yasuo Satoh
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUSES INCLUDING COMMAND DELAY ADJUSTMENT CIRCUIT
- Publication number 20180358064
- Publication date Dec 13, 2018
- Micron Technology, Inc.
- Shuichi Ishibashi
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR ADJUSTING DELAY OF COMMAND SIGNAL PATH
- Publication number 20180286470
- Publication date Oct 4, 2018
- Micron Technology, Inc.
- Kazutaka Miyano
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR ADJUSTING DELAY OF COMMAND SIGNAL PATH
- Publication number 20180053538
- Publication date Feb 22, 2018
- Micron Technology, Inc.
- Kazutaka Miyano
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUSES INCLUDING COMMAND DELAY ADJUSTMENT CIRCUIT
- Publication number 20170309323
- Publication date Oct 26, 2017
- Micron Technology, Inc.
- Shuichi Ishibashi
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUSES INCLUDING COMMAND DELAY ADJUSTMENT CIRCUIT
- Publication number 20170309320
- Publication date Oct 26, 2017
- Micron Technology, Inc.
- Shuichi Ishibashi
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUSES INCLUDING COMMAND LATENCY CONTROL CIRCUIT
- Publication number 20160322964
- Publication date Nov 3, 2016
- Micron Technology, Inc.
- Kazutaka Miyano
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
OUTPUT SIGNAL GENERATING DEVICE, SEMICONDUCTOR DEVICE AND OUTPUT SI...
- Publication number 20150364181
- Publication date Dec 17, 2015
- PS4 LUXCO S.A.R.L.
- Kazutaka Miyano
- G11 - INFORMATION STORAGE
Information Patent Application
Clock generating circuit, semiconductor device including the same,...
- Publication number 20150214962
- Publication date Jul 30, 2015
- PS4 LUXCO S.A.R.L.
- Kazutaka Miyano
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING TH...
- Publication number 20150103608
- Publication date Apr 16, 2015
- PS4 LUXCO S.A.R.L.
- Kazutaka Miyano
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20150043299
- Publication date Feb 12, 2015
- Micron Technology, Inc.
- Kazutaka Miyano
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20140232438
- Publication date Aug 21, 2014
- Elpida Memory, Inc.
- Kazutaka Miyano
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME
- Publication number 20140021994
- Publication date Jan 23, 2014
- Elpida Memory, Inc.
- Hitoshi TANAKA
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME
- Publication number 20130194035
- Publication date Aug 1, 2013
- Elpida Memory, Inc.
- Hitoshi TANAKA
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
CLOCK GENERATING CIRCUIT, SEMICONDUCTOR DEVICE INCLUDING THE SAME,...
- Publication number 20120134223
- Publication date May 31, 2012
- Elpida Memory, Inc.
- Kazutaka Miyano
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Semiconductor device and information processing system including th...
- Publication number 20120120745
- Publication date May 17, 2012
- Elpida Memory, Inc.
- Kazutaka Miyano
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE HAVING DLL CIRCUIT
- Publication number 20120124409
- Publication date May 17, 2012
- ELPIDA MEMORY, INC.
- Kazutaka Miyano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME
- Publication number 20120112829
- Publication date May 10, 2012
- Elpida Memory, Inc.
- Hitoshi TANAKA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTERNAL-CLOCK ADJUSTING CIRCUIT
- Publication number 20110227618
- Publication date Sep 22, 2011
- Elpida Memory, Inc.
- Kazutaka Miyano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor device having level shift circuit, control method the...
- Publication number 20110062998
- Publication date Mar 17, 2011
- Elpida Memory, Inc.
- Shingo Mitsubori
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock generating circuit, semiconductor device including the same,...
- Publication number 20110058437
- Publication date Mar 10, 2011
- Elpida Memory, Inc.
- Kazutaka Miyano
- H03 - BASIC ELECTRONIC CIRCUITRY

Kazutaka Miyano

Person

Patents Grantslast 30 patents

Apparatuses and methods for deactivating a delay locked loop update...

Selectively controlling clock transmission to a data (DQ) system

Apparatuses and methods for adjusting delay of command signal path

Apparatuses and methods for deactivating a delay locked loop update...

Apparatuses and methods for data transmission offset values in burs...

Shifter circuits having registers arranged in a folded topology

Selectively controlling clock transmission to a data (DQ) system

Methods and apparatuses including command delay adjustment circuit

Techniques for command synchronization in a memory device

Shifter circuits having registers arranged in a folded topology

Apparatuses and methods for data transmission offset values in burs...

Techniques for command synchronization in a memory device

Methods and apparatuses including command delay adjustment circuit

Apparatuses and methods for adjusting delay of command signal path

Methods and apparatuses including command delay adjustment circuit

Output signal generation device having a phase adjustment unit and...

Methods and apparatuses including command latency control circuit

Clock generating circuit, semiconductor device including the same,...

Semiconductor device

Semiconductor device

Clock generating circuit, semiconductor device including the same,...

Semiconductor device and information processing system including an...

Semiconductor device having DLL circuit

Semiconductor device and method of controlling the same

Internal-clock adjusting circuit

DLL circuit, semiconductor device including the same, and data proc...

Semiconductor device and method of controlling the same

Clock generating circuit, semiconductor device including the same,...

Semiconductor device having level shift circuit, control method the...

Clock control circuit and semiconductor device including the same

Patents Applicationslast 30 patents

Apparatuses And Methods For Deactivating A Delay Locked Loop Update...

SELECTIVELY CONTROLLING CLOCK TRANSMISSION TO A DATA (DQ) SYSTEM

APPARATUSES AND METHODS FOR DEACTIVATING A DELAY LOCKED LOOP UPDATE...

SHIFTER CIRCUITS HAVING REGISTERS ARRANGED IN A FOLDED TOPOLOGY

SELECTIVELY CONTROLLING CLOCK TRANSMISSION TO A DATA (DQ) SYSTEM

APPARATUSES AND METHODS FOR DATA TRANSMISSION OFFSET VALUES IN BURS...

SHIFTER CIRCUITS HAVING REGISTERS ARRANGED IN A FOLDED TOPOLOGY

TECHNIQUES FOR COMMAND SYNCHRONIZATION IN A MEMORY DEVICE

TECHNIQUES FOR COMMAND SYNCHRONIZATION IN A MEMORY DEVICE

APPARATUSES AND METHODS FOR DATA TRANSMISSION OFFSET VALUES IN BURS...

METHODS AND APPARATUSES INCLUDING COMMAND DELAY ADJUSTMENT CIRCUIT

APPARATUSES AND METHODS FOR ADJUSTING DELAY OF COMMAND SIGNAL PATH

APPARATUSES AND METHODS FOR ADJUSTING DELAY OF COMMAND SIGNAL PATH

METHODS AND APPARATUSES INCLUDING COMMAND DELAY ADJUSTMENT CIRCUIT

METHODS AND APPARATUSES INCLUDING COMMAND DELAY ADJUSTMENT CIRCUIT

METHODS AND APPARATUSES INCLUDING COMMAND LATENCY CONTROL CIRCUIT

OUTPUT SIGNAL GENERATING DEVICE, SEMICONDUCTOR DEVICE AND OUTPUT SI...

Clock generating circuit, semiconductor device including the same,...

SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING TH...

SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME

SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME

CLOCK GENERATING CIRCUIT, SEMICONDUCTOR DEVICE INCLUDING THE SAME,...

Semiconductor device and information processing system including th...

SEMICONDUCTOR DEVICE HAVING DLL CIRCUIT

SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME

INTERNAL-CLOCK ADJUSTING CIRCUIT

Semiconductor device having level shift circuit, control method the...

Clock generating circuit, semiconductor device including the same,...