Keerthinarayan P. Heragu

Person

Irving, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Efficient implementation of a multiplier/accumulator with load
- Patent number 10,146,506
- Issue date Dec 4, 2018
- Texas Instruments Incorporated
- Darrell E. Tinker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance implementation of the FFT butterfly computation
- Patent number 9,672,192
- Issue date Jun 6, 2017
- Texas Instruments Incorporated
- Darrell E. Tinker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for accelerating simulations and designing int...
- Patent number 8,301,431
- Issue date Oct 30, 2012
- Texas Instruments Incorporated
- Keerthinarayan P. Heragu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power controller, a method of operating the power controller and a...
- Patent number 8,266,464
- Issue date Sep 11, 2012
- Texas Instruments Incorporated
- Michael P. Clinton
- G11 - INFORMATION STORAGE
Information Patent Grant
Master slave delay locked loops and uses thereof
- Patent number 7,932,756
- Issue date Apr 26, 2011
- Texas Instruments Incorporated
- Keerthinarayan P. Heragu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Glitch reduced delay lock loop circuits and methods for using such
- Patent number 7,719,332
- Issue date May 18, 2010
- Texas Instruments Incorporated
- Keerthinarayan P. Heragu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for reduced area delay locked loop
- Patent number 7,573,307
- Issue date Aug 11, 2009
- Texas Instruments Incorporated
- Keerthinarayan P. Heragu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Glitch reduced compensated circuits and methods for using such
- Patent number 7,550,993
- Issue date Jun 23, 2009
- Texas Instruments Incorporated
- Keerthinarayan P. Heragu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and systems to reduce data skew in FIFOs
- Patent number 7,216,247
- Issue date May 8, 2007
- Texas Instruments Incorporated
- Keerthinarayan P. Heragu
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-timed strobe generator and method for use with multi-strobe ra...
- Patent number 6,930,953
- Issue date Aug 16, 2005
- Texas Instruments Incorporated
- Keerthinarayan P. Heragu
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for generating charge sharing test vectors
- Patent number 6,553,547
- Issue date Apr 22, 2003
- Texas Instruments Incorporated
- Keerthinarayan P. Heragu
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
EFFICIENT IMPLEMENTATION OF A MULTIPLIER/ACCUMULATOR WITH LOAD
- Publication number 20160132295
- Publication date May 12, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Darrell E. Tinker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE IMPLEMENTATION OF THE FFT BUTTERFLY COMPUTATION
- Publication number 20160132461
- Publication date May 12, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Darrell E. Tinker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR ACCELERATING SIMULATIONS AND DESIGNING INT...
- Publication number 20090177451
- Publication date Jul 9, 2009
- TEXAS INSTRUMENTS INCORPORATED
- KEERTHINARAYAN P. HERAGU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLITCH REDUCED COMPENSATED CIRCUITS AND METHODS FOR USING SUCH
- Publication number 20090051390
- Publication date Feb 26, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Keerthinarayan P. Heragu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Glitch Reduced Delay Lock Loop Circuits and Methods for Using Such
- Publication number 20090033385
- Publication date Feb 5, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Keerthinarayan P. Heragu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Master Slave Delay Locked Loops and Uses Thereof
- Publication number 20090033387
- Publication date Feb 5, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Keerthinarayan P. Heragu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Systems and Methods for Reduced Area Delay Locked Loop
- Publication number 20090033388
- Publication date Feb 5, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Keerthinarayan P. Heragu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Delay Lock Loop Circuits Including Glitch Reduction and Methods for...
- Publication number 20090033386
- Publication date Feb 5, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Padattil K. Nisha
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
POWER CONTROLLER, A METHOD OF OPERATING THE POWER CONTROLLER AND A...
- Publication number 20080098244
- Publication date Apr 24, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Michael P. Clinton
- G11 - INFORMATION STORAGE
Information Patent Application
Methods and systems to reduce data skew in FIFOs
- Publication number 20060031703
- Publication date Feb 9, 2006
- Keerthinarayan P. Heragu
- G11 - INFORMATION STORAGE
Information Patent Application
Method to test memories that operate at twice their nominal bandwidth
- Publication number 20050144525
- Publication date Jun 30, 2005
- Keerthinarayan Heragu
- G11 - INFORMATION STORAGE
Information Patent Application
Self-timed strobe generator and method for use with multi-strobe ra...
- Publication number 20040052153
- Publication date Mar 18, 2004
- Keerthinarayan P. Heragu
- G11 - INFORMATION STORAGE

Keerthinarayan P. Heragu

Person

Patents Grantslast 30 patents

Efficient implementation of a multiplier/accumulator with load

High performance implementation of the FFT butterfly computation

Apparatus and method for accelerating simulations and designing int...

Power controller, a method of operating the power controller and a...

Master slave delay locked loops and uses thereof

Glitch reduced delay lock loop circuits and methods for using such

Systems and methods for reduced area delay locked loop

Glitch reduced compensated circuits and methods for using such

Methods and systems to reduce data skew in FIFOs

Self-timed strobe generator and method for use with multi-strobe ra...

Method and system for generating charge sharing test vectors

Patents Applicationslast 30 patents

EFFICIENT IMPLEMENTATION OF A MULTIPLIER/ACCUMULATOR WITH LOAD

HIGH PERFORMANCE IMPLEMENTATION OF THE FFT BUTTERFLY COMPUTATION

APPARATUS AND METHOD FOR ACCELERATING SIMULATIONS AND DESIGNING INT...

GLITCH REDUCED COMPENSATED CIRCUITS AND METHODS FOR USING SUCH

Glitch Reduced Delay Lock Loop Circuits and Methods for Using Such

Master Slave Delay Locked Loops and Uses Thereof

Systems and Methods for Reduced Area Delay Locked Loop

Delay Lock Loop Circuits Including Glitch Reduction and Methods for...

POWER CONTROLLER, A METHOD OF OPERATING THE POWER CONTROLLER AND A...

Methods and systems to reduce data skew in FIFOs

Method to test memories that operate at twice their nominal bandwidth

Self-timed strobe generator and method for use with multi-strobe ra...