Kei-Yong Khoo

Person

Berkeley, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and system for automated script generation for EDA tools
- Patent number 8,875,087
- Issue date Oct 28, 2014
- Cadence Design Systems, Inc.
- Yinghua Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for creating a boolean model of multi-path and mu...
- Patent number 8,132,135
- Issue date Mar 6, 2012
- Cadence Design Systems, Inc.
- Kei-Yong Khoo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for creating a boolean model of multi-path and mu...
- Patent number 7,735,035
- Issue date Jun 8, 2010
- Cadence Design Systems, Inc.
- Kei-Yong Khoo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for equivalence checking of a low power design
- Patent number 7,669,165
- Issue date Feb 23, 2010
- Cadence Design Systems, Inc.
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for verification of circuits with encoded signals
- Patent number 7,627,842
- Issue date Dec 1, 2009
- Cadence Design Systems, Inc.
- Kei-Yong Khoo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for logic equivalence checking
- Patent number 7,620,919
- Issue date Nov 17, 2009
- Cadence Design Systems, Inc.
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for logic equivalence checking
- Patent number 7,620,918
- Issue date Nov 17, 2009
- Cadence Design Systems, Inc.
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for selection and replacement of subcircuits in e...
- Patent number 7,373,618
- Issue date May 13, 2008
- Cadence Design Systems, Inc.
- Kei-Yong Khoo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for logic equivalence checking
- Patent number 7,266,790
- Issue date Sep 4, 2007
- Cadence Design Systems, Inc.
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND SYSTEM FOR CREATING A BOOLEAN MODEL OF MULTI-PATH AND MU...
- Publication number 20090113363
- Publication date Apr 30, 2009
- Cadence Design Systems, Inc.
- Kei-Yong KHOO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for equivalence checking of a low power design
- Publication number 20080127014
- Publication date May 29, 2008
- Cadence Design Systems, Inc.
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and System for Logic Equivalence Checking
- Publication number 20070294650
- Publication date Dec 20, 2007
- Cadence Design Systems, Inc.
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and System for Logic Equivalence Checking
- Publication number 20070294649
- Publication date Dec 20, 2007
- Cadence Design Systems, Inc.
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for logic equivalence checking
- Publication number 20040177332
- Publication date Sep 9, 2004
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING

Kei-Yong Khoo

Person

Patents Grantslast 30 patents

Method and system for automated script generation for EDA tools

Method and system for creating a boolean model of multi-path and mu...

Method and system for creating a boolean model of multi-path and mu...

Method and system for equivalence checking of a low power design

Method and system for verification of circuits with encoded signals

Method and system for logic equivalence checking

Method and system for logic equivalence checking

Method and system for selection and replacement of subcircuits in e...

Method and system for logic equivalence checking

Patents Applicationslast 30 patents

METHOD AND SYSTEM FOR CREATING A BOOLEAN MODEL OF MULTI-PATH AND MU...

Method and system for equivalence checking of a low power design

Method and System for Logic Equivalence Checking

Method and System for Logic Equivalence Checking

Method and system for logic equivalence checking