Keishi SAKANUSHI

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Kanagawa-ken, JP

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Patents Grantslast 30 patents

Information Patent Grant
Non-volatile memory device having 3D memory cell array with improve...
- Patent number 9,190,150
- Issue date Nov 17, 2015
- Kabushiki Kaisha Toshiba
- Keishi Sakanushi
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for generating circuit layout using design mod...
- Patent number 9,158,878
- Issue date Oct 13, 2015
- Kabushiki Kaisha Toshiba
- Keishi Sakanushi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout correcting method, recording medium and design layout correc...
- Patent number 8,972,907
- Issue date Mar 3, 2015
- Kabushiki Kaisha Toshiba
- Yoko Yokoyama
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DETECTION METHOD OF ALGORITHM IN INTEGRATED CIRCUIT
- Publication number 20150260768
- Publication date Sep 17, 2015
- KABUSHIKI KAISHA TOSHIBA
- Keishi SAKANUSHI
- G01 - MEASURING TESTING
Information Patent Application
DESIGN LAYOUT CORRECTING METHOD, RECORDING MEDIUM AND DESIGN LAYOUT...
- Publication number 20150074618
- Publication date Mar 12, 2015
- KABUSHIKI KAISHA TOSHIBA
- Yoko Yokoyama
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR INTEGRATED CIRCUIT DESIGN LAYOUT SUPPORT BY COMPUTER AND...
- Publication number 20150058816
- Publication date Feb 26, 2015
- KABUSHIKI KAISHA TOSHIBA
- Keishi SAKANUSHI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE
- Publication number 20140293700
- Publication date Oct 2, 2014
- KABUSHIKI KAISHA TOSHIBA
- Keishi SAKANUSHI
- G11 - INFORMATION STORAGE