Keith A. Bowman

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Sequential circuit with error detection
- Patent number 10,024,916
- Issue date Jul 17, 2018
- Intel Corporation
- Keith A. Bowman
- G01 - MEASURING TESTING
Information Patent Grant
Resilient register file circuit for dynamic variation tolerance and...
- Patent number 9,772,903
- Issue date Sep 26, 2017
- Intel Corporation
- Jaydeep P. Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Grant
Sequential circuit with error detection
- Patent number 9,594,625
- Issue date Mar 14, 2017
- Intel Corporation
- Keith A. Bowman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Resilient register file circuit for dynamic variation tolerance and...
- Patent number 9,329,918
- Issue date May 3, 2016
- Intel Corporation
- Jaydeep P. Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-contained, path-level aging monitor apparatus and method
- Patent number 9,229,054
- Issue date Jan 5, 2016
- Intel Corporation
- Keith A. Bowman
- G01 - MEASURING TESTING
Information Patent Grant
Sequential circuit with error detection
- Patent number 9,189,014
- Issue date Nov 17, 2015
- Intel Corporation
- Keith A. Bowman
- G01 - MEASURING TESTING
Information Patent Grant
Sequential circuit with error detection
- Patent number 8,301,970
- Issue date Oct 30, 2012
- Intel Corporation
- Keith Bowman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay fault detection using latch with error sampling
- Patent number 7,653,850
- Issue date Jan 26, 2010
- Intel Corporation
- James W. Tschanz
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SEQUENTIAL CIRCUIT WITH ERROR DETECTION
- Publication number 20170139006
- Publication date May 18, 2017
- Intel Corporation
- Keith A. Bowman
- G01 - MEASURING TESTING
Information Patent Application
RESILIENT REGISTER FILE CIRCUIT FOR DYNAMIC VARIATION TOLERANCE AND...
- Publication number 20160210192
- Publication date Jul 21, 2016
- Intel Corporation
- Jaydeep P. Kulkarni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEQUENTIAL CIRCUIT WITH ERROR DETECTION
- Publication number 20160034338
- Publication date Feb 4, 2016
- Intel Corporation
- Keith A. Bowman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Sequential Circuit with Error Detection
- Publication number 20140122947
- Publication date May 1, 2014
- Keith A. Bowman
- G01 - MEASURING TESTING
Information Patent Application
RESILIENT REGISTER FILE CIRCUIT FOR DYNAMIC VARIATION TOLERANCE AND...
- Publication number 20140032980
- Publication date Jan 30, 2014
- Jaydeep P. Kulkarni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELF-CONTAINED, PATH-LEVEL AGING MONITOR APPARATUS AND METHOD
- Publication number 20130285685
- Publication date Oct 31, 2013
- Keith A. Bowman
- G01 - MEASURING TESTING
Information Patent Application
Sequential circuit with error detection
- Publication number 20100079184
- Publication date Apr 1, 2010
- Keith Bowman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DELAY FAULT DETECTION USING LATCH WITH ERROR SAMPLING
- Publication number 20080307277
- Publication date Dec 11, 2008
- James W. Tschanz
- G06 - COMPUTING CALCULATING COUNTING

Keith A. Bowman

Person

Patents Grantslast 30 patents

Sequential circuit with error detection

Resilient register file circuit for dynamic variation tolerance and...

Sequential circuit with error detection

Resilient register file circuit for dynamic variation tolerance and...

Self-contained, path-level aging monitor apparatus and method

Sequential circuit with error detection

Sequential circuit with error detection

Delay fault detection using latch with error sampling

Patents Applicationslast 30 patents

SEQUENTIAL CIRCUIT WITH ERROR DETECTION

RESILIENT REGISTER FILE CIRCUIT FOR DYNAMIC VARIATION TOLERANCE AND...

SEQUENTIAL CIRCUIT WITH ERROR DETECTION

Sequential Circuit with Error Detection

RESILIENT REGISTER FILE CIRCUIT FOR DYNAMIC VARIATION TOLERANCE AND...

SELF-CONTAINED, PATH-LEVEL AGING MONITOR APPARATUS AND METHOD

Sequential circuit with error detection

DELAY FAULT DETECTION USING LATCH WITH ERROR SAMPLING