Keith E. Zawadzki

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Moisture hermetic guard ring for semiconductor on insulator devices
- Patent number 12,014,996
- Issue date Jun 18, 2024
- Intel Corporation
- Mohammad Kabir
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra-abrupt semiconductor junction profile
- Patent number 8,394,687
- Issue date Mar 12, 2013
- Intel Corporation
- Pushkar Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming improved EPI fill on narrow isolation bounded so...
- Patent number 7,691,752
- Issue date Apr 6, 2010
- Intel Corporation
- Pushkar Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS device with dual-epi channels and self-aligned contacts
- Patent number 7,598,142
- Issue date Oct 6, 2009
- Pushkar Ranade
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DESIGN LITHOGRAPHIC SEAM IMPLEMENTATION METHODOLOGY F...
- Publication number 20250112167
- Publication date Apr 3, 2025
- Intel Corporation
- Kimberly Pierce
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIDUCIALS WITH UNDERLYING DUMMY METALLIZATION FOR INTEGRATED CIRCUI...
- Publication number 20250006652
- Publication date Jan 2, 2025
- Intel Corporation
- Omkar G. Karhade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIDUCIALS WITH ASSOCIATED LOW-DENSITY METAL ZONES
- Publication number 20250006653
- Publication date Jan 2, 2025
- Intel Corporation
- Omkar G. Karhade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THROUGH-SILICON VIA DIE
- Publication number 20240363490
- Publication date Oct 31, 2024
- Intel Corporation
- Mohammad Enamul KABIR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS TO REDUCE STRESS IN INTEGRATED CIRCUIT PACKAGES
- Publication number 20240347590
- Publication date Oct 17, 2024
- Intel Corporation
- Bhaskar Jyoti Krishnatreya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED RING STRUCTURES
- Publication number 20240145383
- Publication date May 2, 2024
- Intel Corporation
- June Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MOISTURE HERMETIC GUARD RING FOR SEMICONDUCTOR ON INSULATOR DEVICES
- Publication number 20240145410
- Publication date May 2, 2024
- Intel Corporation
- Mohammad Kabir
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HERMETIC BARRIER SURROUNDING A PLURALITY OF DIES
- Publication number 20230197638
- Publication date Jun 22, 2023
- Mohammad Enamul KABIR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HERMETIC SEAL FOR TRANSISTORS WITH METAL ON BOTH SIDES
- Publication number 20230197538
- Publication date Jun 22, 2023
- Intel Corporation
- Mohammad Enamul KABIR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MOISTURE HERMETIC GUARD RING FOR SEMICONDUCTOR ON INSULATOR DEVICES
- Publication number 20210407932
- Publication date Dec 30, 2021
- Intel Corporation
- Mohammad Kabir
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RAISED FACET- AND NON-FACET 3D SOURCE/DRAIN CONTACTS IN MOSFETS
- Publication number 20090315120
- Publication date Dec 24, 2009
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING NITRIDE STRESSING LAYER FOR REPLACEMENT METAL GA...
- Publication number 20090085097
- Publication date Apr 2, 2009
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CARBON CONTROLLED FIXED CHARGE PROCESS
- Publication number 20090011581
- Publication date Jan 8, 2009
- Cory E. Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING IMPROVED EPI FILL ON NARROW ISOLATION BOUNDED SO...
- Publication number 20080237741
- Publication date Oct 2, 2008
- Pushkar Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING IMPROVED EPI FILL ON NARROW ISOLATION BOUNDED SO...
- Publication number 20080237742
- Publication date Oct 2, 2008
- Pushkar Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA-ABRUPT SEMICONDUCTOR JUNCTION PROFILE
- Publication number 20080237661
- Publication date Oct 2, 2008
- Pushkar Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS device with dual-EPI channels and self-aligned contacts
- Publication number 20080227250
- Publication date Sep 18, 2008
- Pushkar Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Carbon controlled fixed charge process
- Publication number 20070077739
- Publication date Apr 5, 2007
- Cory E. Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PMOS transistor strain optimization with raised junction regions
- Publication number 20070034945
- Publication date Feb 15, 2007
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PMOS transistor strain optimization with raised junction regions
- Publication number 20040262683
- Publication date Dec 30, 2004
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS

Keith E. Zawadzki

Person

Patents Grantslast 30 patents

Moisture hermetic guard ring for semiconductor on insulator devices

Ultra-abrupt semiconductor junction profile

Methods of forming improved EPI fill on narrow isolation bounded so...

CMOS device with dual-epi channels and self-aligned contacts

Patents Applicationslast 30 patents

SEMICONDUCTOR DESIGN LITHOGRAPHIC SEAM IMPLEMENTATION METHODOLOGY F...

FIDUCIALS WITH UNDERLYING DUMMY METALLIZATION FOR INTEGRATED CIRCUI...

FIDUCIALS WITH ASSOCIATED LOW-DENSITY METAL ZONES

THROUGH-SILICON VIA DIE

METHODS AND APPARATUS TO REDUCE STRESS IN INTEGRATED CIRCUIT PACKAGES

INTEGRATED RING STRUCTURES

MOISTURE HERMETIC GUARD RING FOR SEMICONDUCTOR ON INSULATOR DEVICES

HERMETIC BARRIER SURROUNDING A PLURALITY OF DIES

HERMETIC SEAL FOR TRANSISTORS WITH METAL ON BOTH SIDES

MOISTURE HERMETIC GUARD RING FOR SEMICONDUCTOR ON INSULATOR DEVICES

RAISED FACET- AND NON-FACET 3D SOURCE/DRAIN CONTACTS IN MOSFETS

METHODS OF FORMING NITRIDE STRESSING LAYER FOR REPLACEMENT METAL GA...

CARBON CONTROLLED FIXED CHARGE PROCESS

METHODS OF FORMING IMPROVED EPI FILL ON NARROW ISOLATION BOUNDED SO...

METHODS OF FORMING IMPROVED EPI FILL ON NARROW ISOLATION BOUNDED SO...

ULTRA-ABRUPT SEMICONDUCTOR JUNCTION PROFILE

CMOS device with dual-EPI channels and self-aligned contacts

Carbon controlled fixed charge process

PMOS transistor strain optimization with raised junction regions

PMOS transistor strain optimization with raised junction regions