Keith M. Bindloss

Person

Irvine, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Processing system with interspersed processors DMA-FIFO
- Patent number 12,197,970
- Issue date Jan 14, 2025
- HyperX Logic, Inc.
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory-network processor with programmable optimizations
- Patent number 11,900,124
- Issue date Feb 13, 2024
- Coherent Logix, Incorporated
- Michael B Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory network processor
- Patent number 11,829,320
- Issue date Nov 28, 2023
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory network processor
- Patent number 11,550,750
- Issue date Jan 10, 2023
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory-network processor with programmable optimizations
- Patent number 11,544,072
- Issue date Jan 3, 2023
- Coherent Logix, Inc.
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor instructions to accelerate FEC encoding and decoding
- Patent number 11,327,753
- Issue date May 10, 2022
- Coherent Logix, Incorporated
- Keith M. Bindloss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing system with interspersed processors DMA-FIFO
- Patent number 11,030,023
- Issue date Jun 8, 2021
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory-network processor with programmable optimizations
- Patent number 11,016,779
- Issue date May 25, 2021
- Coherent Logix, Incorporated
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory network processor
- Patent number 10,747,709
- Issue date Aug 18, 2020
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor instructions to accelerate FEC encoding and decoding
- Patent number 10,691,451
- Issue date Jun 23, 2020
- Coherent Logix, Incorporated
- Keith M. Bindloss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory-network processor with programmable optimizations
- Patent number 9,430,369
- Issue date Aug 30, 2016
- Coherent Logix, Incorporated
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing system with interspersed processors DMA-FIFO
- Patent number 9,424,213
- Issue date Aug 23, 2016
- Coherent Logix, Incorporated
- Carl S. Dobbs
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and system for execution and latching of data in alternate t...
- Patent number 7,428,653
- Issue date Sep 23, 2008
- Mindspeed Technologies, Inc.
- Duncan M. Fisher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, systems, and computer program products for translating mac...
- Patent number 7,266,811
- Issue date Sep 4, 2007
- Conexant Systems, Inc.
- Moataz Mohamed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for efficient operation of a very long instruction word digi...
- Patent number 6,684,319
- Issue date Jan 27, 2004
- Conexant Systems, Inc.
- Moataz A. Mohamed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Space vector data path
- Patent number 5,778,241
- Issue date Jul 7, 1998
- Rockwell International Corporation
- Keith M. Bindloss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Triple register RISC digital signal processor
- Patent number 5,586,284
- Issue date Dec 17, 1996
- Rockwell International Corporation
- Keith M. Bindloss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-chip debug port
- Patent number 5,544,311
- Issue date Aug 6, 1996
- Rockwell International Corporation
- Donald D. Harenberg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal processor contexts with elemental and reserved group addressing
- Patent number 5,479,626
- Issue date Dec 26, 1995
- Rockwell International Corporation
- Keith M. Bindloss
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS DMA-FIFO
- Publication number 20250117271
- Publication date Apr 10, 2025
- HyperX Logic, Inc.
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS
- Publication number 20230153117
- Publication date May 18, 2023
- Coherent Logix, Incorporated
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Network Processor
- Publication number 20230061478
- Publication date Mar 2, 2023
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processing System With Interspersed Processors DMA-FIFO
- Publication number 20210326193
- Publication date Oct 21, 2021
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS
- Publication number 20210208895
- Publication date Jul 8, 2021
- Coherent Logix, Incorporated
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Network Processor
- Publication number 20210034566
- Publication date Feb 4, 2021
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor Instructions to Accelerate FEC Encoding and Decoding
- Publication number 20200319880
- Publication date Oct 8, 2020
- Coherent Logix, Incorporated
- Keith M. Bindloss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory-Network Processor with Programmable Optimizations
- Publication number 20190369990
- Publication date Dec 5, 2019
- Coherent Logix, Incorporated
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Network Processor
- Publication number 20190138492
- Publication date May 9, 2019
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor Instructions to Accelerate FEC Encoding and Decoding
- Publication number 20170185399
- Publication date Jun 29, 2017
- Coherent Logix, Incorporated
- Keith M. Bindloss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processing System With Interspersed Processors DMA-FIFO
- Publication number 20160335207
- Publication date Nov 17, 2016
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS
- Publication number 20160328231
- Publication date Nov 10, 2016
- Coherent Logix, Incorporated
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS
- Publication number 20140351551
- Publication date Nov 27, 2014
- Coherent Logix, Incorporated
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processing System With Interspersed Processors DMA-FIFO
- Publication number 20140143470
- Publication date May 22, 2014
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Alternate multi-threaded pipeline
- Publication number 20060020841
- Publication date Jan 26, 2006
- Conexant Systems, Inc.
- Duncan M. Fisher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods, systems, and computer program products for translating mac...
- Publication number 20030046669
- Publication date Mar 6, 2003
- Moataz Mohamed
- G06 - COMPUTING CALCULATING COUNTING

Keith M. Bindloss

Person

Patents Grantslast 30 patents

Processing system with interspersed processors DMA-FIFO

Memory-network processor with programmable optimizations

Memory network processor

Memory network processor

Memory-network processor with programmable optimizations

Processor instructions to accelerate FEC encoding and decoding

Processing system with interspersed processors DMA-FIFO

Memory-network processor with programmable optimizations

Memory network processor

Processor instructions to accelerate FEC encoding and decoding

Memory-network processor with programmable optimizations

Processing system with interspersed processors DMA-FIFO

Method and system for execution and latching of data in alternate t...

Methods, systems, and computer program products for translating mac...

System for efficient operation of a very long instruction word digi...

Space vector data path

Triple register RISC digital signal processor

On-chip debug port

Signal processor contexts with elemental and reserved group addressing

Patents Applicationslast 30 patents

PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS DMA-FIFO

MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS

Memory Network Processor

Processing System With Interspersed Processors DMA-FIFO

MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS

Memory Network Processor

Processor Instructions to Accelerate FEC Encoding and Decoding

Memory-Network Processor with Programmable Optimizations

Memory Network Processor

Processor Instructions to Accelerate FEC Encoding and Decoding

Processing System With Interspersed Processors DMA-FIFO

MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS

MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS

Processing System With Interspersed Processors DMA-FIFO

Alternate multi-threaded pipeline

Methods, systems, and computer program products for translating mac...