Kelvin Kwan

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and systems for energy efficiency and energy conservation in...
- Patent number 10,725,524
- Issue date Jul 28, 2020
- Intel Corporation
- Jawad Nasrullah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for flushing dirty cache lines based on cache...
- Patent number 9,965,023
- Issue date May 8, 2018
- Intel Corporation
- David Keppel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for energy efficiency and energy conservation i...
- Patent number 9,665,144
- Issue date May 30, 2017
- Intel Corporation
- Jawad Nasrullah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling power gate circuitry based on dynamic capacitance of a...
- Patent number 9,594,412
- Issue date Mar 14, 2017
- Intel Corporation
- Vjekoslav Svilan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for reduced core entry into a power state havi...
- Patent number 9,442,849
- Issue date Sep 13, 2016
- Intel Corporation
- David Keppel
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and systems for energy efficiency and energy conservation in...
- Patent number 9,280,190
- Issue date Mar 8, 2016
- Intel Corporation
- Jawad Nasrullah
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Semiconductor chip with adaptive BIST cache testing during runtime
- Patent number 9,229,872
- Issue date Jan 5, 2016
- Intel Corporation
- Christopher Wilkerson
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHOD FOR REDUCED CORE ENTRY INTO A POWER STATE HAVI...
- Publication number 20170003734
- Publication date Jan 5, 2017
- Intel Corporation
- DAVID KEPPEL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEMS FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION IN...
- Publication number 20160179175
- Publication date Jun 23, 2016
- Intel Corporation
- Jawad Nasrullah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor Chip With Adaptive BIST Cache Testing During Runtime
- Publication number 20140281254
- Publication date Sep 18, 2014
- Christopher WILKERSON
- G01 - MEASURING TESTING
Information Patent Application
Apparatus and Method For Reduced Core Entry Into A Power State Havi...
- Publication number 20140189240
- Publication date Jul 3, 2014
- David KEPPEL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLING POWER GATE CIRCUITRY BASED ON DYNAMIC CAPACITANCE OF A...
- Publication number 20130275782
- Publication date Oct 17, 2013
- Vjekoslav Svilan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEMS FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION IN...
- Publication number 20120166838
- Publication date Jun 28, 2012
- Jawad Nasrullah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION I...
- Publication number 20120151235
- Publication date Jun 14, 2012
- Jawad Nasrullah
- G06 - COMPUTING CALCULATING COUNTING

Kelvin Kwan

Person

Patents Grantslast 30 patents

Method and systems for energy efficiency and energy conservation in...

Apparatus and method for flushing dirty cache lines based on cache...

Methods and systems for energy efficiency and energy conservation i...

Controlling power gate circuitry based on dynamic capacitance of a...

Apparatus and method for reduced core entry into a power state havi...

Method and systems for energy efficiency and energy conservation in...

Semiconductor chip with adaptive BIST cache testing during runtime

Patents Applicationslast 30 patents

APPARATUS AND METHOD FOR REDUCED CORE ENTRY INTO A POWER STATE HAVI...

METHOD AND SYSTEMS FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION IN...

Semiconductor Chip With Adaptive BIST Cache Testing During Runtime

Apparatus and Method For Reduced Core Entry Into A Power State Havi...

CONTROLLING POWER GATE CIRCUITRY BASED ON DYNAMIC CAPACITANCE OF A...

METHOD AND SYSTEMS FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION IN...

METHODS AND SYSTEMS FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION I...