Ken Saito

Person

Tokyo, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatuses for decreasing write pull-up time and methods of use
- Patent number 10,811,081
- Issue date Oct 20, 2020
- Micron Technology, Inc.
- Shinichi Takayama
- G11 - INFORMATION STORAGE
Information Patent Grant
Obtaining power domain by clustering logical blocks based on activa...
- Patent number 8,621,415
- Issue date Dec 31, 2013
- Renesas Electronics Corporation
- Kenta Suto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arrangement verification apparatus
- Patent number 8,122,416
- Issue date Feb 21, 2012
- Renesas Electronics Corporation
- Ken Saito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing analysis method, logic synthesis method and circuit partiti...
- Patent number 8,108,809
- Issue date Jan 31, 2012
- Renesas Electronics Corporation
- Toshiyuki Sadakane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Floor plan evaluating method, floor plan correcting method, program...
- Patent number 7,730,439
- Issue date Jun 1, 2010
- Renesas Technology Corp.
- Ken Saito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing analysis method, logic synthesis method and circuit partiti...
- Patent number 7,418,688
- Issue date Aug 26, 2008
- Renesas Technology Corp.
- Toshiyuki Sadakane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic floor-planning method capable of shortening floor-plan pr...
- Patent number 7,017,134
- Issue date Mar 21, 2006
- Renesas Technology Corp.
- Ken Saito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Floorplanning apparatus deciding floor plan using logic seeds assoc...
- Patent number 6,938,232
- Issue date Aug 30, 2005
- Renesas Technology Corp.
- Ken Saito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic cell placement and routing apparatus and automatic cell p...
- Patent number 6,711,726
- Issue date Mar 23, 2004
- Renesas Technology Corp.
- Koji Hirakimoto
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
APPARATUSES FOR DECREASING WRITE PULL-UP TIME AND METHODS OF USE
- Publication number 20200194051
- Publication date Jun 18, 2020
- Micron Technology, Inc.
- Shinichi Takayama
- G11 - INFORMATION STORAGE
Information Patent Application
AUTOMATED APPRAISAL SYSTEM FOR CARDS
- Publication number 20150310506
- Publication date Oct 29, 2015
- JAPAN NOVEL CORPORATION
- Ken-ichi SAITO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT AND PROGRAM THEREFOR
- Publication number 20120216166
- Publication date Aug 23, 2012
- Renesas Electronics Corporation
- Kenta SUTO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARRANGEMENT VERIFICATION APPARATUS
- Publication number 20090259978
- Publication date Oct 15, 2009
- RENESAS TECHNOLOGY CORP.
- Ken SAITO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Floor plan evaluating method, floor plan correcting method, program...
- Publication number 20090024970
- Publication date Jan 22, 2009
- Renesas Technology Corp.
- Ken Saito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Routing analysis method, logic synthesis method and circuit partiti...
- Publication number 20080295055
- Publication date Nov 27, 2008
- Renesas Technology Corp.
- Toshiyuki Sadakane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of treating diabetes by inhibiting degradation of at least o...
- Publication number 20070196354
- Publication date Aug 23, 2007
- Hirofumi Doi
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Application
Inhibition of nerve cell death by inhibiting degradation of shc3, a...
- Publication number 20060264363
- Publication date Nov 23, 2006
- Hirofumi Doi
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Application
Routing analysis method, logic synthesis method and circuit partiti...
- Publication number 20050246676
- Publication date Nov 3, 2005
- Renesas Technology Corp.
- Toshiyuki Sadakane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic floor-planning method capable of shortening floor-plan pr...
- Publication number 20040228167
- Publication date Nov 18, 2004
- Renesas Technology Corp.
- Ken Saito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Floorplanning apparatus deciding floor plan using logic seeds assoc...
- Publication number 20030229874
- Publication date Dec 11, 2003
- Ken Saito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic cell placement and routing apparatus and automatic cell p...
- Publication number 20020046389
- Publication date Apr 18, 2002
- Koji Hirakimoto
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Apparatuses for decreasing write pull-up time and methods of use

Obtaining power domain by clustering logical blocks based on activa...

Arrangement verification apparatus

Routing analysis method, logic synthesis method and circuit partiti...

Floor plan evaluating method, floor plan correcting method, program...

Routing analysis method, logic synthesis method and circuit partiti...

Automatic floor-planning method capable of shortening floor-plan pr...

Floorplanning apparatus deciding floor plan using logic seeds assoc...

Automatic cell placement and routing apparatus and automatic cell p...

Patents Applicationslast 30 patents

APPARATUSES FOR DECREASING WRITE PULL-UP TIME AND METHODS OF USE

AUTOMATED APPRAISAL SYSTEM FOR CARDS

LAYOUT METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT AND PROGRAM THEREFOR

ARRANGEMENT VERIFICATION APPARATUS

Floor plan evaluating method, floor plan correcting method, program...

Routing analysis method, logic synthesis method and circuit partiti...

Method of treating diabetes by inhibiting degradation of at least o...

Inhibition of nerve cell death by inhibiting degradation of shc3, a...

Routing analysis method, logic synthesis method and circuit partiti...

Automatic floor-planning method capable of shortening floor-plan pr...

Floorplanning apparatus deciding floor plan using logic seeds assoc...

Automatic cell placement and routing apparatus and automatic cell p...