Ken Wadland

Person

Grafton, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Deterministic, parallel execution with overlapping regions
- Patent number 8,789,060
- Issue date Jul 22, 2014
- Cadence Design Systems, Inc.
- Ken Wadland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems for automatic circuit routing with object oriented constraints
- Patent number 8,549,459
- Issue date Oct 1, 2013
- Cadence Design Systems, Inc.
- Ken Wadland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and mechanism for implementing PCB routing
- Patent number 8,510,703
- Issue date Aug 13, 2013
- Cadence Design Systems, Inc.
- Ken Wadland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global constraint optimization
- Patent number 8,479,138
- Issue date Jul 2, 2013
- Cadence Design Systems, Inc.
- Randall Scott Lawson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Localized routing direction
- Patent number 8,250,514
- Issue date Aug 21, 2012
- Cadence Design Systems, Inc.
- Ken Wadland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Budgeting global constraints on local constraints in an autorouter
- Patent number 8,191,032
- Issue date May 29, 2012
- Cadence Design Systems, Inc.
- Ken Wadland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for resolving overloads in autorouting physical interconnect...
- Patent number 8,151,239
- Issue date Apr 3, 2012
- Cadence Design Systems, Inc.
- Ken Wadland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for optimized circuit autorouting
- Patent number 8,146,042
- Issue date Mar 27, 2012
- Cadence Design Systems, Inc.
- Ken Wadland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for resolving overloads in autorouting physical interconnect...
- Patent number 8,086,987
- Issue date Dec 27, 2011
- Cadence Design Systems, Inc.
- Ken Wadland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for resolving overloads in autorouting physical interconnect...
- Patent number 8,082,533
- Issue date Dec 20, 2011
- Cadence Design Systems, Inc.
- Ken Wadland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and mechanism for implementing automated PCB routing
- Patent number 7,937,681
- Issue date May 3, 2011
- Cadence Design Systems, Inc.
- Ken Wadland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for adaptive bundling of connections in user-guid...
- Patent number 7,793,249
- Issue date Sep 7, 2010
- Cadence Design Systems, Inc.
- Ken Wadland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit autorouter with object oriented constraints
- Patent number 7,761,836
- Issue date Jul 20, 2010
- Cadence Design Systems, Inc.
- Ken Wadland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for optimized circuit autorouting
- Patent number 7,620,922
- Issue date Nov 17, 2009
- Cadence Design Systems, Inc.
- Ken Wadland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for optimized automated IC package pin routing
- Patent number 7,594,215
- Issue date Sep 22, 2009
- Cadence Design Systems, Inc.
- Ken Wadland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementing deterministic multi-processing
- Patent number 7,574,686
- Issue date Aug 11, 2009
- Cadence Design Systems, Inc.
- Ken Wadland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Budgeting global constraints on local constraints in an autorouter
- Patent number 7,562,330
- Issue date Jul 14, 2009
- Cadence Design Systems, Inc.
- Ken Wadland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
User-guided autorouting
- Patent number 7,536,665
- Issue date May 19, 2009
- Cadence Design Systems, Inc.
- Greg Horlick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for resolving overloads in autorouting physical interconnect...
- Patent number 7,464,358
- Issue date Dec 9, 2008
- Cadence Design Systems, Inc.
- Ken Wadland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Topological global routing for automated IC package interconnect
- Patent number 7,017,137
- Issue date Mar 21, 2006
- Cadence Design Systems, Inc.
- Ken Wadland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Topological global routing for automated IC package interconnect
- Patent number 6,516,447
- Issue date Feb 4, 2003
- Cadence Design Systems, Inc.
- Ken Wadland
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Method and mechanism for implementing automated PCB routing
- Publication number 20060242614
- Publication date Oct 26, 2006
- Cadence Design Systems, Inc.
- Ken Wadland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for optimized automated IC package pin routing
- Publication number 20060112366
- Publication date May 25, 2006
- Cadence Design Systems, Inc.
- Ken Wadland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Topological global routing for automated IC package interconnect
- Publication number 20030126578
- Publication date Jul 3, 2003
- Cadence Design Systems, Inc.
- Ken Wadland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TOPOLOGICAL GLOBAL ROUTING FOR AUTOMATED IC PACKAGE INTERCONNECT
- Publication number 20030009738
- Publication date Jan 9, 2003
- Ken Wadland
- G06 - COMPUTING CALCULATING COUNTING

Ken Wadland

Person

Patents Grantslast 30 patents

Deterministic, parallel execution with overlapping regions

Systems for automatic circuit routing with object oriented constraints

Method and mechanism for implementing PCB routing

Global constraint optimization

Localized routing direction

Budgeting global constraints on local constraints in an autorouter

Method for resolving overloads in autorouting physical interconnect...

Method and system for optimized circuit autorouting

Method for resolving overloads in autorouting physical interconnect...

Method for resolving overloads in autorouting physical interconnect...

Method and mechanism for implementing automated PCB routing

Method and system for adaptive bundling of connections in user-guid...

Circuit autorouter with object oriented constraints

Method and system for optimized circuit autorouting

Method and system for optimized automated IC package pin routing

Method and system for implementing deterministic multi-processing

Budgeting global constraints on local constraints in an autorouter

User-guided autorouting

Method for resolving overloads in autorouting physical interconnect...

Topological global routing for automated IC package interconnect

Topological global routing for automated IC package interconnect

Patents Applicationslast 30 patents

Method and mechanism for implementing automated PCB routing

Method and system for optimized automated IC package pin routing

Topological global routing for automated IC package interconnect

TOPOLOGICAL GLOBAL ROUTING FOR AUTOMATED IC PACKAGE INTERCONNECT