Keng-Hua KUO

Person

Hsinchu, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit layout generation method and system
- Patent number 12,135,930
- Issue date Nov 5, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ke-Ying Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit layout generation method
- Patent number 11,907,636
- Issue date Feb 20, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ke-Ying Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit layout generation method and system
- Patent number 11,842,135
- Issue date Dec 12, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ke-Ying Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit layout generation method and system
- Patent number 11,392,749
- Issue date Jul 19, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ke-Ying Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit modeling methods and systems
- Patent number 10,846,456
- Issue date Nov 24, 2020
- Taiwan Semiconductor Manufacturing Company Ltd.
- Ke-Ying Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit layout generation method and system
- Patent number 10,796,059
- Issue date Oct 6, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ke-Ying Su
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT LAYOUT GENERATION METHOD AND SYSTEM
- Publication number 20240386181
- Publication date Nov 21, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ke-Ying SU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT LAYOUT GENERATION METHOD
- Publication number 20240160828
- Publication date May 16, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ke-Ying SU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT LAYOUT GENERATION METHOD AND SYSTEM
- Publication number 20240111935
- Publication date Apr 4, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ke-Ying SU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT LAYOUT GENERATION METHOD
- Publication number 20220343054
- Publication date Oct 27, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ke-Ying SU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT LAYOUT GENERATION METHOD AND SYSTEM
- Publication number 20210073454
- Publication date Mar 11, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ke-Ying SU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT LAYOUT GENERATION METHOD AND SYSTEM
- Publication number 20210019467
- Publication date Jan 21, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ke-Ying SU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT MODELING METHODS AND SYSTEMS
- Publication number 20190340328
- Publication date Nov 7, 2019
- Taiwan Semiconductor Manufacturing company Ltd.
- Ke-Ying SU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT LAYOUT GENERATION METHOD AND SYSTEM
- Publication number 20190294750
- Publication date Sep 26, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ke-Ying SU
- G06 - COMPUTING CALCULATING COUNTING

Keng-Hua KUO

Person

Patents Grantslast 30 patents

Integrated circuit layout generation method and system

Integrated circuit layout generation method

Integrated circuit layout generation method and system

Integrated circuit layout generation method and system

Integrated circuit modeling methods and systems

Integrated circuit layout generation method and system

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT LAYOUT GENERATION METHOD AND SYSTEM

INTEGRATED CIRCUIT LAYOUT GENERATION METHOD

INTEGRATED CIRCUIT LAYOUT GENERATION METHOD AND SYSTEM

INTEGRATED CIRCUIT LAYOUT GENERATION METHOD

INTEGRATED CIRCUIT LAYOUT GENERATION METHOD AND SYSTEM

INTEGRATED CIRCUIT LAYOUT GENERATION METHOD AND SYSTEM

INTEGRATED CIRCUIT MODELING METHODS AND SYSTEMS

INTEGRATED CIRCUIT LAYOUT GENERATION METHOD AND SYSTEM