Kenneth A. Dockser

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Floating-point processor with operand-format precision greater than...
- Patent number 6,029,243
- Issue date Feb 22, 2000
- VLSI Technology, Inc.
- Timothy A. Pontius
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor with programmable instruction trap for deimplementin...
- Patent number 6,006,030
- Issue date Dec 21, 1999
- VLSI Technology, Inc.
- Kenneth A. Dockser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for efficiently implementing complex function...
- Patent number 5,963,454
- Issue date Oct 5, 1999
- VLSI Technology, Inc.
- Kenneth A. Dockser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processor system with instruction substitution filter for deim...
- Patent number 5,862,370
- Issue date Jan 19, 1999
- VLSI Technology, Inc.
- Kenneth A. Dockser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data-packet fifo buffer system with end-of-packet flags
- Patent number 5,860,119
- Issue date Jan 12, 1999
- VLSI Technology, Inc.
- Kenneth A. Dockser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wrapped-line cache for microprocessor system
- Patent number 5,845,308
- Issue date Dec 1, 1998
- VLSI Technology, Inc.
- Ken A. Dockser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for computer implemented constant multiplicati...
- Patent number 5,841,684
- Issue date Nov 24, 1998
- VLSI Technology, Inc.
- Kenneth A. Dockser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer-implemented multiplication with shifting of pattern-produc...
- Patent number 5,815,422
- Issue date Sep 29, 1998
- VLSI Technology, Inc.
- Kenneth A. Dockser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Zero-run-length encoder with shift register
- Patent number 5,764,357
- Issue date Jun 9, 1998
- VLSI Technology, Inc.
- Kenneth A. Dockser
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Von Neumann system with harvard processor and instruction buffer
- Patent number 5,706,466
- Issue date Jan 6, 1998
- VLSI Technology, Inc.
- Kenneth A. Dockser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor with instruction-cycle versus clock-frequency mode s...
- Patent number 5,649,174
- Issue date Jul 15, 1997
- VLSI Technology Inc.
- Kenneth A. Dockser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processor with flexible register mapping scheme
- Patent number 5,613,151
- Issue date Mar 18, 1997
- Kenneth A. Dockser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arithmetic logic unit with zero-result prediction
- Patent number 5,604,689
- Issue date Feb 18, 1997
- VLSI Technology, Inc.
- Kenneth A. Dockser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor system having instruction cache with reserved branch...
- Patent number 5,603,045
- Issue date Feb 11, 1997
- VLSI Technology, Inc.
- Kenneth A. Dockser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arithmetic logic unit with zero sum prediction
- Patent number 5,586,069
- Issue date Dec 17, 1996
- VLSI Technology, Inc.
- Kenneth A. Dockser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Floating-point processor with apparent-precision based selection of...
- Patent number 5,481,686
- Issue date Jan 2, 1996
- VLSI Technology, Inc.
- Kenneth A. Dockser
- G06 - COMPUTING CALCULATING COUNTING

Kenneth A. Dockser

Person

Patents Grantslast 30 patents

Floating-point processor with operand-format precision greater than...

Microprocessor with programmable instruction trap for deimplementin...

Method and apparatus for efficiently implementing complex function...

Data processor system with instruction substitution filter for deim...

Data-packet fifo buffer system with end-of-packet flags

Wrapped-line cache for microprocessor system

Method and apparatus for computer implemented constant multiplicati...

Computer-implemented multiplication with shifting of pattern-produc...

Zero-run-length encoder with shift register

Von Neumann system with harvard processor and instruction buffer

Microprocessor with instruction-cycle versus clock-frequency mode s...

Data processor with flexible register mapping scheme

Arithmetic logic unit with zero-result prediction

Microprocessor system having instruction cache with reserved branch...

Arithmetic logic unit with zero sum prediction

Floating-point processor with apparent-precision based selection of...