Kenneth A. Poteet

Person

Houston, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
High-speed memory arranged for operating synchronously with a micro...
- Patent number 6,088,280
- Issue date Jul 11, 2000
- Texas Instruments Incorporated
- Wilbur Christian Vogley
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed memory arranged for operating synchronously with a micro...
- Patent number 5,982,694
- Issue date Nov 9, 1999
- Texas Instruments Incorporated
- Wilbur Christian Vogley
- G11 - INFORMATION STORAGE
Information Patent Grant
Data processing system arranged for operating synchronously with a...
- Patent number 5,912,854
- Issue date Jun 15, 1999
- Texas Instruments Incorporated
- Wilbur Christian Vogley
- G11 - INFORMATION STORAGE
Information Patent Grant
Random access memory with latency arranged for operating synchronou...
- Patent number 5,808,958
- Issue date Sep 15, 1998
- Texas Instruments Incorporated
- Wilbur Christian Vogley
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for a memory unit with a processor integrated...
- Patent number 5,678,021
- Issue date Oct 14, 1997
- Texas Instruments Incorporated
- Basavaraj I. Pawate
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Random access memory arranged for operating synchronously with a mi...
- Patent number 5,587,954
- Issue date Dec 24, 1996
- Texas Instruments Incorporated
- Wilbur C. Vogley
- G11 - INFORMATION STORAGE
Information Patent Grant
Process of making and a DRAM standby charge pump with oscillator ha...
- Patent number 5,410,510
- Issue date Apr 25, 1995
- Texas Instruments Inc.
- Scott E. Smith
- G11 - INFORMATION STORAGE
Information Patent Grant
Fuse selectable timing signals for internal signal generators
- Patent number 5,402,390
- Issue date Mar 28, 1995
- Texas Instruments Inc.
- Duc Ho
- G11 - INFORMATION STORAGE
Information Patent Grant
System including a data processor, a synchronous dram, a peripheral...
- Patent number 5,390,149
- Issue date Feb 14, 1995
- Texas Instruments Incorporated
- Wilbur C. Vogley
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual receiver edge-triggered digital signal level detection system
- Patent number 5,347,184
- Issue date Sep 13, 1994
- Texas Instruments Incorporated
- Michael C. Stephens
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for implementing .times.2 parity DRAM for 16 b...
- Patent number 5,287,311
- Issue date Feb 15, 1994
- Texas Instruments Incorporated
- Jim C. Tso
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory module arranged for data and parity bits
- Patent number 5,228,132
- Issue date Jul 13, 1993
- Texas Instrument Incorporated
- Joseph H. Neal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory module arranged for data and parity bits
- Patent number 5,089,993
- Issue date Feb 18, 1992
- Texas Instruments Incorporated
- Joseph H. Neal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detector and integrated circuit device including charge pump circui...
- Patent number 5,075,572
- Issue date Dec 24, 1991
- Texas Instruments Incorporated
- Kenneth A. Poteet
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic memory with intermediate column derode
- Patent number 4,630,240
- Issue date Dec 16, 1986
- Texas Instruments Incorporated
- Ken A. Poteet
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier circuit for dynamic read/write memory
- Patent number 4,555,777
- Issue date Nov 26, 1985
- Texas Instruments Incorporated
- Ken A. Poteet
- G11 - INFORMATION STORAGE

Kenneth A. Poteet

Person

Patents Grantslast 30 patents

High-speed memory arranged for operating synchronously with a micro...

High speed memory arranged for operating synchronously with a micro...

Data processing system arranged for operating synchronously with a...

Random access memory with latency arranged for operating synchronou...

Apparatus and method for a memory unit with a processor integrated...

Random access memory arranged for operating synchronously with a mi...

Process of making and a DRAM standby charge pump with oscillator ha...

Fuse selectable timing signals for internal signal generators

System including a data processor, a synchronous dram, a peripheral...

Dual receiver edge-triggered digital signal level detection system

Method and apparatus for implementing .times.2 parity DRAM for 16 b...

Memory module arranged for data and parity bits

Memory module arranged for data and parity bits

Detector and integrated circuit device including charge pump circui...

Dynamic memory with intermediate column derode

Sense amplifier circuit for dynamic read/write memory