Kenneth E. Merryman

Person

Fridley, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for selectively providing hierarchy to a circu...
- Patent number 6,718,520
- Issue date Apr 6, 2004
- Unisys Corporation
- Kenneth E. Merryman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Spreadsheet driven I/O buffer synthesis process
- Patent number 6,708,144
- Issue date Mar 16, 2004
- Unisys Corporation
- Kenneth E. Merryman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for incremntally optimizing a circuit design
- Patent number 6,026,220
- Issue date Feb 15, 2000
- Unisys Corporation
- Kevin C. Cleereman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for optimizing a gated clock structure using a...
- Patent number 5,980,092
- Issue date Nov 9, 1999
- Unisys Corporation
- Kenneth E. Merryman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for providing optimization parameters to a log...
- Patent number 5,960,184
- Issue date Sep 28, 1999
- Unisys Corporation
- Kevin C. Cleereman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for optimizing a circuit design having multi-p...
- Patent number 5,956,256
- Issue date Sep 21, 1999
- Unisys Corporation
- James E. Rezek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for monitoring the performance of a circuit op...
- Patent number 5,940,604
- Issue date Aug 17, 1999
- Unisys Corporation
- Kenneth E. Merryman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for identifying gated clocks within a circuit...
- Patent number 5,864,487
- Issue date Jan 26, 1999
- Unisys Corporation
- Kenneth E. Merryman
- G06 - COMPUTING CALCULATING COUNTING

Kenneth E. Merryman

Person

Patents Grantslast 30 patents

Method and apparatus for selectively providing hierarchy to a circu...

Spreadsheet driven I/O buffer synthesis process

Method and apparatus for incremntally optimizing a circuit design

Method and apparatus for optimizing a gated clock structure using a...

Method and apparatus for providing optimization parameters to a log...

Method and apparatus for optimizing a circuit design having multi-p...

Method and apparatus for monitoring the performance of a circuit op...

Method and apparatus for identifying gated clocks within a circuit...