Kenneth M. Key

Person

Raleigh, NC, US

People

Patents Grantslast 30 patents

Information Patent Grant
System and method for operating a packet buffer in an intermediate...
- Patent number 8,180,966
- Issue date May 15, 2012
- Cisco Technology, Inc.
- Kenneth M. Key
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable arrayed processing engine architecture for a network s...
- Patent number 7,895,412
- Issue date Feb 22, 2011
- Cisco Tehnology, Inc.
- Darren Kerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture for a processor complex of an arrayed pipelined proces...
- Patent number 7,380,101
- Issue date May 27, 2008
- Cisco Technology, Inc.
- Michael L. Wright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor isolation technique for integrated multi-processor systems
- Patent number 7,185,224
- Issue date Feb 27, 2007
- Cisco Technology, Inc.
- William Fredenburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for operating a packet buffer
- Patent number 6,892,285
- Issue date May 10, 2005
- Cisco Technology, Inc.
- Kenneth M. Key
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Electronic system modeling using actual and approximated system pro...
- Patent number 6,876,961
- Issue date Apr 5, 2005
- Cisco Technology, Inc.
- John W. Marshall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for processing memory requests
- Patent number 6,851,028
- Issue date Feb 1, 2005
- Cisco Technology, Inc.
- Kwok Ken Mak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture for a processor complex of an arrayed pipelined proces...
- Patent number 6,836,838
- Issue date Dec 28, 2004
- Cisco Technology, Inc.
- Michael L. Wright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor isolation method for integrated multi-processor systems
- Patent number 6,681,341
- Issue date Jan 20, 2004
- Cisco Technology, Inc.
- William Fredenburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable processing engine for efficiently processing transient...
- Patent number 6,513,108
- Issue date Jan 28, 2003
- Cisco Technology, Inc.
- Darren Kerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture for a process complex of an arrayed pipelined processi...
- Patent number 6,442,669
- Issue date Aug 27, 2002
- Cisco Technology, Inc.
- Michael L. Wright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing of replicated components of electronic device
- Patent number 6,385,747
- Issue date May 7, 2002
- Cisco Technology, Inc.
- Jeffery Burl Scott
- G11 - INFORMATION STORAGE
Information Patent Grant
Pooled receive and transmit queues to access a shared bus in a mult...
- Patent number 6,356,548
- Issue date Mar 12, 2002
- Cisco Technology, Inc.
- Scott Nellenbach
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Synchronization and control system for an arrayed processing engine
- Patent number 6,272,621
- Issue date Aug 7, 2001
- Cisco Technology, Inc.
- Kenneth Michael Key
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for passing data among processor complex stage...
- Patent number 6,195,739
- Issue date Feb 27, 2001
- Cisco Technology, Inc.
- Michael L. Wright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel processor with debug capability
- Patent number 6,173,386
- Issue date Jan 9, 2001
- Cisco Technology, Inc.
- Kenneth Michael Key
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronization and control system for an arrayed processing engine
- Patent number 6,119,215
- Issue date Sep 12, 2000
- Cisco Technology, Inc.
- Kenneth Michael Key
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for context switching between processing elements in a pipel...
- Patent number 6,101,599
- Issue date Aug 8, 2000
- Cisco Technology, Inc.
- Michael L. Wright
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
System and method for operating a packet buffer in an intermediate...
- Publication number 20050169291
- Publication date Aug 4, 2005
- Kenneth M. Key
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Architecture for a processor complex of an arrayed pipelined proces...
- Publication number 20050125643
- Publication date Jun 9, 2005
- Michael L. Wright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Architecture for a processor complex of an arrayed pipelined proces...
- Publication number 20010000046
- Publication date Mar 15, 2001
- Michael L. Wright
- G06 - COMPUTING CALCULATING COUNTING

Kenneth M. Key

Person

Patents Grantslast 30 patents

System and method for operating a packet buffer in an intermediate...

Programmable arrayed processing engine architecture for a network s...

Architecture for a processor complex of an arrayed pipelined proces...

Processor isolation technique for integrated multi-processor systems

System and method for operating a packet buffer

Electronic system modeling using actual and approximated system pro...

System and method for processing memory requests

Architecture for a processor complex of an arrayed pipelined proces...

Processor isolation method for integrated multi-processor systems

Programmable processing engine for efficiently processing transient...

Architecture for a process complex of an arrayed pipelined processi...

Testing of replicated components of electronic device

Pooled receive and transmit queues to access a shared bus in a mult...

Synchronization and control system for an arrayed processing engine

Method and apparatus for passing data among processor complex stage...

Parallel processor with debug capability

Synchronization and control system for an arrayed processing engine

System for context switching between processing elements in a pipel...

Patents Applicationslast 30 patents

System and method for operating a packet buffer in an intermediate...

Architecture for a processor complex of an arrayed pipelined proces...

Architecture for a processor complex of an arrayed pipelined proces...