Kenneth Mednick

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Method and system for implementing parallel processing of electroni...
- Patent number 7,904,852
- Issue date Mar 8, 2011
- Cadence Design Systems, Inc.
- Eitan Cadouri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementing parallel processing of electroni...
- Patent number 7,823,095
- Issue date Oct 26, 2010
- Cadence Design Systems, Inc.
- Eitan Cadouri
Information Patent Grant
IC layout physical verification method
- Patent number 7,243,321
- Issue date Jul 10, 2007
- Cadence Design Systems, Inc.
- Xiaojun Wang
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
IC layout physical verification method
- Publication number 20050229126
- Publication date Oct 13, 2005
- Xiaojun Wang
- G06 - COMPUTING CALCULATING COUNTING