Kent Donald Moat

Person

Winfield, IL, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for nested instruction looping using implicit...
- Patent number 7,945,768
- Issue date May 17, 2011
- Motorola Mobility, Inc.
- Raymond B. Essick, IV
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for battery-aware dynamic bandwidth allocation...
- Patent number 7,801,079
- Issue date Sep 21, 2010
- Motorola, Inc.
- Ali Saidi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory address generation with non-harmonic indexing
- Patent number 7,502,909
- Issue date Mar 10, 2009
- Motorola, Inc.
- Kent D. Moat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for elimination of prolog and epilog instructi...
- Patent number 7,415,601
- Issue date Aug 19, 2008
- Motorola, Inc.
- Philip E. May
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dataflow graph compression for power reduction in a vector processor
- Patent number 7,290,122
- Issue date Oct 30, 2007
- Motorola, Inc.
- Philip E. May
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Component interconnect with self-clocking data
- Patent number 7,289,528
- Issue date Oct 30, 2007
- Motorola, Inc.
- Kent D. Moat
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Data processing system using multiple addressing modes for SIMD ope...
- Patent number 7,275,148
- Issue date Sep 25, 2007
- FREESCALE SEMICONDUCTOR, INC.
- William C. Moyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Queuing cache for vectors with elements in predictable order
- Patent number 7,246,203
- Issue date Jul 17, 2007
- Motorola, Inc.
- Kent D. Moat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus filter for memory address translation
- Patent number 7,219,209
- Issue date May 15, 2007
- Motorola, Inc.
- Raymond B. Essick, IV
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming vector processor with reconfigurable interconnection switch
- Patent number 7,159,099
- Issue date Jan 2, 2007
- Motorola, Inc.
- Brian Geoffrey Lucas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheduler of program instructions for streaming vector processor ha...
- Patent number 7,140,019
- Issue date Nov 21, 2006
- Motorola, Inc.
- Philip E. May
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for addressing a vector of elements in a parti...
- Patent number 7,100,019
- Issue date Aug 29, 2006
- Motorola, Inc.
- James M. Norris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of programming linear graphs for streaming vector computation
- Patent number 6,934,938
- Issue date Aug 23, 2005
- Motorola, Inc.
- Philip E. May
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnection device with integrated storage
- Patent number 6,850,536
- Issue date Feb 1, 2005
- Motorola, Inc.
- Philip E. May
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory interface with fractional addressing
- Patent number 6,799,261
- Issue date Sep 28, 2004
- Motorola, Inc.
- Philip E. May
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Method and Apparatus for Nested Instruction Looping Using Implicit...
- Publication number 20090307472
- Publication date Dec 10, 2009
- MOTOROLA, INC.
- Raymond B. Essick IV
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Reducing Buffer Overflow Exploits by Compu...
- Publication number 20080250499
- Publication date Oct 9, 2008
- MOTOROLA, INC.
- Kent D. Moat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR BATTERY-AWARE DYNAMIC BANDWIDTH ALLOCATION...
- Publication number 20080211666
- Publication date Sep 4, 2008
- MOTOROLA, INC.
- Ali Saidi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Memory address generation with non-harmonic indexing
- Publication number 20070083729
- Publication date Apr 12, 2007
- Kent D. Moat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Queuing cache for vectors with elements in predictable order
- Publication number 20060112229
- Publication date May 25, 2006
- Kent D. Moat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Data processing system using multiple addressing modes for SIMD ope...
- Publication number 20050055535
- Publication date Mar 10, 2005
- William C. Moyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bus filter for memory address translation
- Publication number 20050050297
- Publication date Mar 3, 2005
- Raymond B. Essick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Component interconnect with self-clocking data
- Publication number 20050047430
- Publication date Mar 3, 2005
- Kent D. Moat
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Dataflow graph compression for power reduction in a vector processor
- Publication number 20050050300
- Publication date Mar 3, 2005
- Philip E. May
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for elimination of prolog and epilog instructi...
- Publication number 20040128473
- Publication date Jul 1, 2004
- Philip E. May
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Partitioned vector processing
- Publication number 20040117595
- Publication date Jun 17, 2004
- James M. Norris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of programming linear graphs for streaming vector computation
- Publication number 20040003376
- Publication date Jan 1, 2004
- Philip E. May
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scheduler for streaming vector processor
- Publication number 20040003220
- Publication date Jan 1, 2004
- Philip E. May
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interconnection device with integrated storage
- Publication number 20040003200
- Publication date Jan 1, 2004
- Philip E. May
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
STREAMING VECTOR PROCESSOR WITH RECONFIGURABLE INTERCONNECTION SWITCH
- Publication number 20040003206
- Publication date Jan 1, 2004
- Philip E. May
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory interface with fractional addressing
- Publication number 20040003199
- Publication date Jan 1, 2004
- Philip E. May
- G06 - COMPUTING CALCULATING COUNTING

Kent Donald Moat

Person

Patents Grantslast 30 patents

Method and apparatus for nested instruction looping using implicit...

Method and apparatus for battery-aware dynamic bandwidth allocation...

Memory address generation with non-harmonic indexing

Method and apparatus for elimination of prolog and epilog instructi...

Dataflow graph compression for power reduction in a vector processor

Component interconnect with self-clocking data

Data processing system using multiple addressing modes for SIMD ope...

Queuing cache for vectors with elements in predictable order

Bus filter for memory address translation

Streaming vector processor with reconfigurable interconnection switch

Scheduler of program instructions for streaming vector processor ha...

Method and apparatus for addressing a vector of elements in a parti...

Method of programming linear graphs for streaming vector computation

Interconnection device with integrated storage

Memory interface with fractional addressing

Patents Applicationslast 30 patents

Method and Apparatus for Nested Instruction Looping Using Implicit...

Method and Apparatus for Reducing Buffer Overflow Exploits by Compu...

METHOD AND APPARATUS FOR BATTERY-AWARE DYNAMIC BANDWIDTH ALLOCATION...

Memory address generation with non-harmonic indexing

Queuing cache for vectors with elements in predictable order

Data processing system using multiple addressing modes for SIMD ope...

Bus filter for memory address translation

Component interconnect with self-clocking data

Dataflow graph compression for power reduction in a vector processor

Method and apparatus for elimination of prolog and epilog instructi...

Partitioned vector processing

Method of programming linear graphs for streaming vector computation

Scheduler for streaming vector processor

Interconnection device with integrated storage

STREAMING VECTOR PROCESSOR WITH RECONFIGURABLE INTERCONNECTION SWITCH

Memory interface with fractional addressing