Ker-Min Chen

Person

Hsinchu City, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Intellectual property recommending method and system
- Patent number 11,615,494
- Issue date Mar 28, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ker-Min Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic application-rule checker
- Patent number 8,943,453
- Issue date Jan 27, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ker-Min Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device with two or more bond pad connections for each...
- Patent number 8,501,622
- Issue date Aug 6, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ker Min Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit having input/output cell array having single gat...
- Patent number 8,492,795
- Issue date Jul 23, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ker-Min Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low leakage voltage level shifting circuit
- Patent number 7,884,643
- Issue date Feb 8, 2011
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Guang-Cheng Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for automatically routing multi-voltage multi-pitch metal lines
- Patent number 7,865,852
- Issue date Jan 4, 2011
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ker-Min Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for setup/hold characterization in sequential cells
- Patent number 7,795,939
- Issue date Sep 14, 2010
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ker-Min Chen
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor device with two or more bond pad connections for each...
- Patent number 7,714,362
- Issue date May 11, 2010
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ker-Min Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ESD protection system for multiple-domain integrated circuits
- Patent number 7,649,214
- Issue date Jan 19, 2010
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ker-Min Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra fine pitch I/O design for microchips
- Patent number 7,594,198
- Issue date Sep 22, 2009
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ker-Min Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Serpentine ballasting resistors for multi-finger ESD protection device
- Patent number 7,557,413
- Issue date Jul 7, 2009
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ker-Min Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for reducing design cycle time for designing inpu...
- Patent number 7,500,214
- Issue date Mar 3, 2009
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ker-Min Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ESD protection system for multi-power domain circuitry
- Patent number 7,420,789
- Issue date Sep 2, 2008
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ker-Min Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ESD protection system for multi-power domain circuitry
- Patent number 7,417,837
- Issue date Aug 26, 2008
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ker-Min Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual voltage single gate oxide I/O circuit with high voltage stress...
- Patent number 7,362,136
- Issue date Apr 22, 2008
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ker-Min Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for inter-chip wireless communication
- Patent number 7,330,702
- Issue date Feb 12, 2008
- Taiwan Semiconductor Manufacturing Co., Ltd
- Ker-Min Chen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Regenerative power-on control circuit
- Patent number 7,295,052
- Issue date Nov 13, 2007
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ker-Min Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Gate-coupled ESD protection circuit for high voltage tolerant I/O
- Patent number 7,274,544
- Issue date Sep 25, 2007
- Taiwan Semiconductor Manufacturing Company
- Ker-Min Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-voltage three-state buffer circuit with simplified tri-state l...
- Patent number 7,248,076
- Issue date Jul 24, 2007
- Taiwan Semiconductor Manufacturing Company
- Kuo-Ji Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Tie-high and tie-low circuit
- Patent number 7,221,183
- Issue date May 22, 2007
- Taiwan Semiconductor Manufacturing Company
- Ker-Min Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cascaded gate-driven ESD clamp
- Patent number 7,221,551
- Issue date May 22, 2007
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ker Min Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single gate oxide I/O buffer with improved under-drive feature
- Patent number 7,193,441
- Issue date Mar 20, 2007
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Kuo-Ji Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Input buffer structure with single gate oxide
- Patent number 7,173,472
- Issue date Feb 6, 2007
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Kuo-Ji Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Built-in test circuit for an integrated circuit device
- Patent number 7,168,021
- Issue date Jan 23, 2007
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ker-Min Chen
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit for level-shifting voltage levels
- Patent number 7,151,391
- Issue date Dec 19, 2006
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ker-Min Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Boost-biased level shifter
- Patent number 7,151,400
- Issue date Dec 19, 2006
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ker-Min Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High-voltage-tolerant feedback coupled I/O buffer
- Patent number 7,142,017
- Issue date Nov 28, 2006
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ker Min Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor device and method of manufacture thereof with two or...
- Patent number 7,071,561
- Issue date Jul 4, 2006
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ker-Min Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for reducing design cycle time for designing inpu...
- Patent number 7,062,740
- Issue date Jun 13, 2006
- Taiwan Semiconductor Manufacturing Co., Ltd
- Ker-Min Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit to eliminate bus contention at chip power up
- Patent number 6,563,353
- Issue date May 13, 2003
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ker-Min Chen
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
INTELLECTUAL PROPERTY RECOMMENDING METHOD AND SYSTEM
- Publication number 20210390644
- Publication date Dec 16, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ker-Min Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT HAVING INPUT/OUTPUT CELL ARRAY HAVING SINGLE GAT...
- Publication number 20130194004
- Publication date Aug 1, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ker-Min CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Automatic Application-Rule Checker
- Publication number 20110055778
- Publication date Mar 3, 2011
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ker-Min Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor Device with Two or More Bond Pad Connections for Each...
- Publication number 20100190299
- Publication date Jul 29, 2010
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ker-Min Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and System for Setup/Hold Characterization in Sequential Cells
- Publication number 20100164583
- Publication date Jul 1, 2010
- Ker-Min Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low Leakage Voltage Level Shifting Circuit
- Publication number 20100026366
- Publication date Feb 4, 2010
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Guang-Cheng Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FINE PITCH BOND PAD STRUCTURE
- Publication number 20100013109
- Publication date Jan 21, 2010
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ker-Min Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Automatically Routing Multi-Voltage Multi-Pitch Metal Lines
- Publication number 20090024976
- Publication date Jan 22, 2009
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ker-Min Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Ultra fine pitch I/O design for microchips
- Publication number 20080204113
- Publication date Aug 28, 2008
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ker-Min Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System and Method For Implementing An Online Design Platform For In...
- Publication number 20080184174
- Publication date Jul 31, 2008
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ker-Min Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Serpentine ballasting resistors for multi-finger ESD protection device
- Publication number 20080111193
- Publication date May 15, 2008
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ker-Min Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual voltage single gate oxide I/O circuit with high voltage stress...
- Publication number 20070247190
- Publication date Oct 25, 2007
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ker-Min Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
EDS protection system for multi-power domain circuitry
- Publication number 20070091522
- Publication date Apr 26, 2007
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ker-Min Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ESD protection system for multi-power domain circuitry
- Publication number 20070091523
- Publication date Apr 26, 2007
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ker-Min Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ESD protection system for multiple-domain integrated circuits
- Publication number 20070085144
- Publication date Apr 19, 2007
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ker-Min Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Regenerative power-on control circuit
- Publication number 20070030039
- Publication date Feb 8, 2007
- Taiwan Semiconductor Manufacturing Co.
- Ker-Min Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Semiconductor device with two or more bond pad connections for each...
- Publication number 20060214189
- Publication date Sep 28, 2006
- Ker-Min Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHOD FOR REDUCING DESIGN CYCLE TIME FOR DESIGNING INPU...
- Publication number 20060195811
- Publication date Aug 31, 2006
- Taiwan Semiconductor Manufacturing Co., LTD
- Ker-Min Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Tie-high and tie-low circuit
- Publication number 20060186925
- Publication date Aug 24, 2006
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ker-Min Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dual-voltage three-state buffer circuit with simplified tri-state l...
- Publication number 20060186921
- Publication date Aug 24, 2006
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Kuo-Ji Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus for inter-chip wireless communication
- Publication number 20060172719
- Publication date Aug 3, 2006
- Ker-Min Chen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Built-in Test Circuit for an Integrated Circuit Device
- Publication number 20060174173
- Publication date Aug 3, 2006
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ker-Min Chen
- G01 - MEASURING TESTING
Information Patent Application
Single gate oxide I/O buffer with improved under-drive feature
- Publication number 20060103435
- Publication date May 18, 2006
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Kuo-Ji Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Gate-coupled ESD protection circuit for high voltage tolerant I/O
- Publication number 20060087779
- Publication date Apr 27, 2006
- Ker-Min Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High-voltage-tolerant feedback coupled I/O buffer
- Publication number 20060049847
- Publication date Mar 9, 2006
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ker-Min Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Boost-biased level shifter
- Publication number 20060012415
- Publication date Jan 19, 2006
- Ker-Min Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Cascaded gate-driven ESD clamp
- Publication number 20050275989
- Publication date Dec 15, 2005
- Ker-Min Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device and method of manufacture thereof with two or...
- Publication number 20050269705
- Publication date Dec 8, 2005
- Ker-Min Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit for level-shifting voltage levels
- Publication number 20050258864
- Publication date Nov 24, 2005
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ker-Mih Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
USB interface and testing method thereof
- Publication number 20050097403
- Publication date May 5, 2005
- Ker-Min Chen
- G06 - COMPUTING CALCULATING COUNTING

Ker-Min Chen

Person

Patents Grantslast 30 patents

Intellectual property recommending method and system

Automatic application-rule checker

Semiconductor device with two or more bond pad connections for each...

Integrated circuit having input/output cell array having single gat...

Low leakage voltage level shifting circuit

Method for automatically routing multi-voltage multi-pitch metal lines

Method and system for setup/hold characterization in sequential cells

Semiconductor device with two or more bond pad connections for each...

ESD protection system for multiple-domain integrated circuits

Ultra fine pitch I/O design for microchips

Serpentine ballasting resistors for multi-finger ESD protection device

System and method for reducing design cycle time for designing inpu...

ESD protection system for multi-power domain circuitry

ESD protection system for multi-power domain circuitry

Dual voltage single gate oxide I/O circuit with high voltage stress...

Method and apparatus for inter-chip wireless communication

Regenerative power-on control circuit

Gate-coupled ESD protection circuit for high voltage tolerant I/O

Dual-voltage three-state buffer circuit with simplified tri-state l...

Tie-high and tie-low circuit

Cascaded gate-driven ESD clamp

Single gate oxide I/O buffer with improved under-drive feature

Input buffer structure with single gate oxide

Built-in test circuit for an integrated circuit device

Integrated circuit for level-shifting voltage levels

Boost-biased level shifter

High-voltage-tolerant feedback coupled I/O buffer

Semiconductor device and method of manufacture thereof with two or...

System and method for reducing design cycle time for designing inpu...

Circuit to eliminate bus contention at chip power up

Patents Applicationslast 30 patents

INTELLECTUAL PROPERTY RECOMMENDING METHOD AND SYSTEM

INTEGRATED CIRCUIT HAVING INPUT/OUTPUT CELL ARRAY HAVING SINGLE GAT...

Automatic Application-Rule Checker

Semiconductor Device with Two or More Bond Pad Connections for Each...

Method and System for Setup/Hold Characterization in Sequential Cells

Low Leakage Voltage Level Shifting Circuit

FINE PITCH BOND PAD STRUCTURE

Method for Automatically Routing Multi-Voltage Multi-Pitch Metal Lines

Ultra fine pitch I/O design for microchips

System and Method For Implementing An Online Design Platform For In...

Serpentine ballasting resistors for multi-finger ESD protection device

Dual voltage single gate oxide I/O circuit with high voltage stress...

EDS protection system for multi-power domain circuitry

ESD protection system for multi-power domain circuitry

ESD protection system for multiple-domain integrated circuits

Regenerative power-on control circuit

Semiconductor device with two or more bond pad connections for each...

SYSTEM AND METHOD FOR REDUCING DESIGN CYCLE TIME FOR DESIGNING INPU...

Tie-high and tie-low circuit

Dual-voltage three-state buffer circuit with simplified tri-state l...

Method and apparatus for inter-chip wireless communication

Built-in Test Circuit for an Integrated Circuit Device

Single gate oxide I/O buffer with improved under-drive feature

Gate-coupled ESD protection circuit for high voltage tolerant I/O

High-voltage-tolerant feedback coupled I/O buffer

Boost-biased level shifter

Cascaded gate-driven ESD clamp

Semiconductor device and method of manufacture thereof with two or...

Integrated circuit for level-shifting voltage levels

USB interface and testing method thereof